AMD Am186TMER ユーザーズマニュアル
Interrupt Control Unit
8-27
8.3.13
Poll Register (POLL, Offset 24h)
(Master Mode)
(Master Mode)
When the Poll Register is read, the current interrupt is acknowledged and the next interrupt
takes its place in the Poll Register.
takes its place in the Poll Register.
The Poll Status Register mirrors the current state of the Poll Register, but the Poll Status
Register can be read without affecting the current interrupt request.
Register can be read without affecting the current interrupt request.
Figure 8-16
Poll Register (POLL, offset 24h)
Bit 15: Interrupt Request (IREQ)—Set to 1 if an interrupt is pending. When this bit is set
to 1, the S4–S0 field contains valid data.
to 1, the S4–S0 field contains valid data.
Bits 14–5: Reserved—Set to 0.
Bits 4–0: Poll Status (S4–S0)—Indicates the interrupt type of the highest priority pending
interrupt. Reading the Poll Register acknowledges the highest priority pending interrupt
and enables the next interrupt to advance into the register.
interrupt. Reading the Poll Register acknowledges the highest priority pending interrupt
and enables the next interrupt to advance into the register.
Although the IS bit is set, the interrupt service routine does not begin execution
automatically. The application software must execute the appropriate ISR.
automatically. The application software must execute the appropriate ISR.
15
7
0
S4–S0
IREQ
Reserved