AMD Am186TMER ユーザーズマニュアル
Interrupt Control Unit
8-31
8.4.4
Interrupt Status Register (INTSTS, Offset 30h)
(Slave Mode)
(Slave Mode)
The Interrupt Status Register controls DMA activity when nonmaskable interrupts occur
and indicates the current interrupt status of the three timers.
and indicates the current interrupt status of the three timers.
Figure 8-20
Interrupt Status Register (INTSTS, offset 30h)
The INTSTS Register is set to 0000h on reset.
Bit 15: DMA Halt (DHLT)—When set to 1, halts any DMA activity. Automatically set to 1
when nonmaskable interrupts occur and reset when an IRET instruction is executed.
when nonmaskable interrupts occur and reset when an IRET instruction is executed.
Bits 14–3: Reserved
Bits 2–0: Timer Interrupt Request (TMR2–TMR0)—When set to 1, indicates the
corresponding timer has an interrupt request pending.
corresponding timer has an interrupt request pending.
15
7
0
Reserved
TMR2
TMR1
TMR0
DHLT