AMD Am186TMER ユーザーズマニュアル
DMA Controller
10-8
10.3.5
DMA Source Address High Register
(High Order Bits) (D0SRCH, Offset C2h, D1SRCH, Offset D2h)
(High Order Bits) (D0SRCH, Offset C2h, D1SRCH, Offset D2h)
Each DMA channel maintains a 20-bit destination and a 20-bit source register. Each register
takes up two full 16-bit registers (the high register and the low register) in the peripheral
control block. For each DMA channel to be used, all four registers must be initialized. These
registers can be individually incremented or decremented after each transfer. If word
transfers are performed, the address is incremented or decremented by 2 after each
transfer. If byte transfers are performed, the address is incremented or decremented by 1.
takes up two full 16-bit registers (the high register and the low register) in the peripheral
control block. For each DMA channel to be used, all four registers must be initialized. These
registers can be individually incremented or decremented after each transfer. If word
transfers are performed, the address is incremented or decremented by 2 after each
transfer. If byte transfers are performed, the address is incremented or decremented by 1.
Each register can point into either memory or I/O space. The user must program the upper
four bits to 0000b in order to address the normal 64K I/O space. Because the DMA channels
can perform transfers to or from odd addresses, there is no restriction on values for the
destination and source address registers. Higher transfer rates can be achieved on the
Am186ER microcontroller if all word transfers are performed to or from even addresses so
that accesses occur in single, 16-bit bus cycles.
four bits to 0000b in order to address the normal 64K I/O space. Because the DMA channels
can perform transfers to or from odd addresses, there is no restriction on values for the
destination and source address registers. Higher transfer rates can be achieved on the
Am186ER microcontroller if all word transfers are performed to or from even addresses so
that accesses occur in single, 16-bit bus cycles.
Figure 10-6
DMA Source Address High Register (D0SRCH, D1SRCH, offsets C2h and D2h)
The value of D0SRCH and D1SRCH at reset is undefined.
Bits 15–4: Reserved
Bits 3–0: DMA Source Address High (DSA19–DSA16)—These bits are driven onto
A19–A16 during the read phase of a DMA transfer.
A19–A16 during the read phase of a DMA transfer.
15
7
0
Reserved
DSA19–DSA16