AMD Am186TMER ユーザーズマニュアル

executing NMI interrupt service routine. As with all hardware interrupts, 
the IF (interrupt flag) is cleared when the processor takes the interrupt, 
disabling the maskable interrupt sources. However, if maskable 
interrupts are re-enabled by software in the NMI interrupt service routine 
(via the STI instruction for example), the fact that an NMI is currently in 
service will not have any effect on the priority resolution of maskable 
interrupt requests. For this reason, it is strongly advised that the interrupt 
service routine for NMI does not enable the maskable interrupts.

An NMI transition from Low to High is latched and synchronized 
internally, and it initiates the interrupt at the next instruction boundary. 
To guarantee that the interrupt is recognized, the NMI pin must be 
asserted for at least one CLKOUTA period. Because NMI is rising edge 
sensitive, holding the pin High during reset has no effect on program 
execution.

These pins indicate to the system that a memory access is in progress 
to the corresponding region of the peripheral memory block (either I/O 
or memory address space). The base address of the peripheral memory 
block is programmable. PCS3–PCS0 are held High during a bus hold 
or reset condition.

Unlike the UCS and LCS chip selects, the PCS outputs assert with the 
multiplexed AD address bus. 

Note: PCS4 is not available on the Am186ER and Am188ER 
microcontrollers. Note also that each peripheral chip select asserts over 
a 256-byte address range, which is twice the address range covered by 
peripheral chip selects in the 80C186 and 80C188 microcontrollers.

PCS5—This pin indicates to the system that a memory access is in 
progress to the sixth region of the peripheral memory block (either I/O 
or memory address space). The base address of the peripheral memory 
block is programmable. PCS5 is held High during a bus hold or reset 
condition. It is also held High during reset.

Note: Unlike the UCS and LCS chip selects, the PCS outputs assert 
with the multiplexed AD address bus. Note also that each peripheral 
chip select asserts over a 256-byte address range, which is twice the 
address range covered by peripheral chip selects in the 80C186 and 
80C188 microcontrollers.

A1—When the EX bit in the MCS and PCS Auxiliary Register is 0, this 
pin supplies an internally latched address bit 1 to the system. During a 
bus hold condition, A1 retains its previously latched value.

PCS6—This pin indicates to the system that a memory access is in 
progress to the seventh region of the peripheral memory block (either 
I/O or memory address space). The base address of the peripheral 
memory block is programmable. PCS6 is held High during a bus hold 
or reset condition.