AMD Am186TMER ユーザーズマニュアル
Refresh Control Unit
7-2
7.1.2
Clock Prescaler Register (CDRAM, Offset E2h)
Figure 7-2
Clock Prescaler Register (CDRAM, offset E2h)
The CDRAM Register is undefined on reset.
Bits 15–9: Reserved—Read back as 0.
Bits 8–0: Refresh Counter Reload Value (RC8–RC0)—Contains the value of the desired
clock count interval between refresh cycles. The counter value should not be set to less
than 18 (12h), otherwise there would never be sufficient bus cycles available for the
processor to execute code.
clock count interval between refresh cycles. The counter value should not be set to less
than 18 (12h), otherwise there would never be sufficient bus cycles available for the
processor to execute code.
In Power-Save mode, the refresh counter value must be adjusted to take into account the
reduced processor clock rate.
reduced processor clock rate.
7.1.3
Enable RCU Register (EDRAM, Offset E4h)
Figure 7-3
Enable RCU Register (EDRAM, offset E4h)
The EDRAM Register is set to 0000h on reset.
Bit 15: Enable RCU (E)—Enables the refresh counter unit when set to 1. Clearing the E
bit at any time clears the refresh counter and stops refresh requests, but it does not reset
the refresh address. Set to 0 on reset.
bit at any time clears the refresh counter and stops refresh requests, but it does not reset
the refresh address. Set to 0 on reset.
Bits 14–9: Reserved—Read back as 0.
Bits 8–0: Refresh Count (T8–T0)—This read-only field contains the present value of the
down counter which triggers refresh requests.
down counter which triggers refresh requests.
15
7
0
0 0 0 0 0
0
RC8–RC0
0
15
7
0
0 0 0 0 0
T8–T0
0
E