AMD Am186TMER ユーザーズマニュアル

AMD

Table of Contents

ix

LIST OF FIGURES

Am186ER Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Am188ER Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Basic Functional System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Processor Status Flags Register (FLAGS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Physical Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Memory and I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Supported Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Am186ER Microcontroller Address Bus—Normal Read
and Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

Am186ER Microcontroller—Read and Write with Address Bus Disable
In Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

Am188ER Microcontroller Address Bus—Normal Read and Write Operation . 3-20

Am188ER Microcontroller—Read and Write with Address Bus Disable
In Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

Oscillator Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

Clock Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

Peripheral Control Block Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Peripheral Control Block Relocation Register (RELREG, offset FEh) . . . . . . . . 4-4

Reset Configuration Register (RESCON, offset F6h) . . . . . . . . . . . . . . . . . . . . 4-5

Processor Release Level Register (PRL, offset F4h). . . . . . . . . . . . . . . . . . . . . 4-6

Power-Save Control Register (PDCON, offset F0h) . . . . . . . . . . . . . . . . . . . . . 4-7

Upper Memory Chip Select Register (UMCS, offset A0h) . . . . . . . . . . . . . . . . . 5-4

Low Memory Chip Select Register (LMCS, offset A2h) . . . . . . . . . . . . . . . . . . . 5-6

Midrange Memory Chip Select Register (MMCS, offset A6h) . . . . . . . . . . . . . . 5-8

PCS and MCS Auxiliary Register (MPCS, offset A8h) . . . . . . . . . . . . . . . . . . . 5-10

Peripheral Chip Select Register (PACS, offset A4h) . . . . . . . . . . . . . . . . . . . . 5-12

Internal Memory Chip Select Register (IMCS, offset ACh) . . . . . . . . . . . . . . . . 6-3

Memory Partition Register (MDRAM, offset E0h). . . . . . . . . . . . . . . . . . . . . . . . 7-1

Clock Prescaler Register (CDRAM, offset E2h) . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Enable RCU Register (EDRAM, offset E4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

External Interrupt Acknowledge Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

Fully Nested (Direct) Mode Interrupt Controller Connections . . . . . . . . . . . . . 8-10

Cascade Mode Interrupt Controller Connections . . . . . . . . . . . . . . . . . . . . . . . 8-11

INT0 and INT1 Control Registers (I0CON, I1CON, offsets 38h and 3Ah) . . . . 8-14

INT2 and INT3 Control Registers (I2CON, I3CON, offsets 3Ch and 3Eh) . . . . 8-16

INT4 Control Register (I4CON, offset 40h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17

Timer/DMA Interrupt Control Registers
(TCUCON, DMA0CON, DMA1CON, offsets 32h, 34h, and 36h) . . . . . . . . . . . 8-18

Watchdog Timer Interrupt Control Register (WDCON, offset 42h). . . . . . . . . . 8-19

Serial Port Interrupt Control Register (SPICON, offset 44h) . . . . . . . . . . . . . . 8-20

Interrupt Status Register (INTSTS, offset 30h) . . . . . . . . . . . . . . . . . . . . . . . . 8-21

Interrupt Request Register (REQST, offset 2Eh) . . . . . . . . . . . . . . . . . . . . . . . 8-22

In-Service Register (INSERV, offset 2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23

Priority Mask Register (PRIMSK, offset 2Ah). . . . . . . . . . . . . . . . . . . . . . . . . . 8-24

Interrupt Mask Register (IMASK, offset 28h) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25

Poll Status Register (POLLST, offset 26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26

Poll Register (POLL, offset 24h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27

Example EOI Assembly Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28

End-of-Interrupt Register (EOI, offset 22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28

Timer and DMA Interrupt Control Registers (T0INTCON, T1INTCON,
T2INTCON, DMA0CON, DMA1CON, offsets 32h, 38h, 3Ah, 34h, and 36h) . . 8-30

Interrupt Status Register (INTSTS, offset 30h) . . . . . . . . . . . . . . . . . . . . . . . . 8-31

Interrupt Request Register (REQST, offset 2Eh) . . . . . . . . . . . . . . . . . . . . . . . 8-32

In-Service Register (INSERV, offset 2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33

Priority Mask Register (PRIMSK, offset 2Ah). . . . . . . . . . . . . . . . . . . . . . . . . . 8-34

Interrupt Mask Register (IMASK, offset 28h) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35