Intel 80C196NU ユーザーズマニュアル
8XC196NP, 80C196NU USER’S MANUAL
10-12
10.4.1.2
Preventing EPA Overruns
Any one of the following methods can be used to prevent or recover from an EPA overrun situa-
tion.
tion.
•
Clear EPAx_CON.0
When the overwrite bit (EPAx_CON.0) is zero, the EPA does not consider the captured
edge until the EPAx_TIME register is read and the data in the capture buffer is transferred to
EPAx_TIME. This prevents the situation by ignoring new input capture events when both
the capture buffer and EPAx_TIME contain valid capture times. The OVRx pending bit in
EPA_PEND is set to indicate that an overrun occurred.
edge until the EPAx_TIME register is read and the data in the capture buffer is transferred to
EPAx_TIME. This prevents the situation by ignoring new input capture events when both
the capture buffer and EPAx_TIME contain valid capture times. The OVRx pending bit in
EPA_PEND is set to indicate that an overrun occurred.
•
Enable the OVRx interrupt and read the EPAx_TIME register within the ISR
If this situation occurs, the overrun (OVRx) interrupt will be generated. The OVRx interrupt
will then be acknowledged and its interrupt service routine will read the EPAx_TIME regis-
ter. After the CPU reads the EPAx_TIME register, the buffered data moves from the buffer
to the EPAx_TIME register. This sets the EPA interrupt pending bit.
will then be acknowledged and its interrupt service routine will read the EPAx_TIME regis-
ter. After the CPU reads the EPAx_TIME register, the buffered data moves from the buffer
to the EPAx_TIME register. This sets the EPA interrupt pending bit.
10.4.2 Operating in Compare Mode
When the selected timer value matches the event-time value, the action specified in the control
register occurs (i.e., the pin is set, cleared, or toggled). If the re-enable bit (EPAx_CON.3) is set,
the action reoccurs on every timer match. If the re-enable bit is cleared, the action does not reoc-
cur until a new value is written to the event-time register. See “Programming the Capture/Com-
pare Channels” on page 10-18 for configuration information.
register occurs (i.e., the pin is set, cleared, or toggled). If the re-enable bit (EPAx_CON.3) is set,
the action reoccurs on every timer match. If the re-enable bit is cleared, the action does not reoc-
cur until a new value is written to the event-time register. See “Programming the Capture/Com-
pare Channels” on page 10-18 for configuration information.
In compare mode, you can use the EPA to produce a pulse-width modulated (PWM) output. The
following sections describe four possible methods.
following sections describe four possible methods.
10.4.2.1
Generating a Low-speed PWM Output
You can generate a low-speed, pulse-width modulated output with a single EPA channel and a
standard interrupt service routine. Configure the EPA channel as follows: compare mode, toggle
output, and the compare function re-enabled. Select standard interrupt service, enable the EPA
interrupt, and globally enable interrupts with the EI instruction. When the assigned timer/counter
value matches the value in the event-time register, the EPA toggles the output pin and generates
an interrupt. The interrupt service routine loads a new value into EPAx_TIME.
standard interrupt service routine. Configure the EPA channel as follows: compare mode, toggle
output, and the compare function re-enabled. Select standard interrupt service, enable the EPA
interrupt, and globally enable interrupts with the EI instruction. When the assigned timer/counter
value matches the value in the event-time register, the EPA toggles the output pin and generates
an interrupt. The interrupt service routine loads a new value into EPAx_TIME.