Intel 80C196NU ユーザーズマニュアル
8XC196NP, 80C196NU USER’S MANUAL
Index-2
Baud-rate generator
SIO port, 8-8
BAUD_VALUE, 8-11, C-42
BHE#, 13-3, B-7
BHE#, 13-3, B-7
during bus hold, 13-30
See also write-control signals
See also write-control signals
BIT, defined, 4-2
Bit-test instructions, A-21
Block diagram
Bit-test instructions, A-21
Block diagram
address/data bus, 7-11
clock circuitry, 2-7
core, 2-3
core and peripherals, 2-2
EPA, 10-2
EPORT, 7-13
I/O ports, 7-1, 7-5, 7-11, 7-13, 7-15
SIO port, 8-1, 10-2
clock circuitry, 2-7
core, 2-3
core and peripherals, 2-2
EPA, 10-2
EPORT, 7-13
I/O ports, 7-1, 7-5, 7-11, 7-13, 7-15
SIO port, 8-1, 10-2
Block transfer mode‚ See PTS
BMOV instruction, A-2, A-9, A-51, A-56
BMOVI instruction, A-3, A-9, A-10, A-51, A-56
BR (indirect) instruction, A-2, A-10, A-51, A-57,
BMOV instruction, A-2, A-9, A-51, A-56
BMOVI instruction, A-3, A-9, A-10, A-51, A-56
BR (indirect) instruction, A-2, A-10, A-51, A-57,
A-64
BREQ#, 13-3, 13-30, B-7
Bulletin board system (BBS), 1-9
Bus contention, See address/data bus, contention
Bus controller, 2-5
Bus width, 13-5
Bulletin board system (BBS), 1-9
Bus contention, See address/data bus, contention
Bus controller, 2-5
Bus width, 13-5
8- and 16-bit comparison, 13-18–13-22
and write-control signals, 13-34
CCB0 fetch, 13-17
control bit, 13-11, 13-17
selecting, 13-1
and write-control signals, 13-34
CCB0 fetch, 13-17
control bit, 13-11, 13-17
selecting, 13-1
BUSCON0, C-49, C-52
BUSCON1, C-50, C-52
BUSCON2, C-50, C-52
BUSCON3, C-50, C-52
BUSCON4, C-50, C-52
BUSCON5, C-50, C-53
BUSCONx, 13-10, 13-11, 13-26
BUSCON1, C-50, C-52
BUSCON2, C-50, C-52
BUSCON3, C-50, C-52
BUSCON4, C-50, C-52
BUSCON5, C-50, C-53
BUSCONx, 13-10, 13-11, 13-26
example, 13-12
Bus-hold protocol, 13-1, 13-30–13-33
and code execution, 13-33
and interrupts, 13-33
and reset, See reset
disabling, 13-32
enabling, 13-32
hold latency, 13-32
regaining bus control, 13-33
and interrupts, 13-33
and reset, See reset
disabling, 13-32
enabling, 13-32
hold latency, 13-32
regaining bus control, 13-33
signals, 13-30
See also port 2, BREQ#, HLDA#,
HOLD#
software protection, 13-32
timing parameters, 13-30
timing parameters, 13-30
Byte accesses
and write-control signals, 13-34
BYTE, defined, 4-2
C
Call instructions, A-57, A-64, A-65
Carry (C) flag, 4-5, A-4, A-5, A-11, A-22, A-23,
Carry (C) flag, 4-5, A-4, A-5, A-11, A-22, A-23,
A-24, A-25, A-36
Cascading timers, 10-6
CCBs, 5-6, 5-7, 11-8, 13-11, 13-14
CCBs, 5-6, 5-7, 11-8, 13-11, 13-14
fetching, 13-14, 13-17, 13-26
CCR0, 12-2
CCRs, 5-7, 11-8, 12-6, 12-7, 13-14
Chip configuration, See CCBs, CCRs
Chip select, 13-1
CCRs, 5-7, 11-8, 12-6, 12-7, 13-14
Chip configuration, See CCBs, CCRs
Chip select, 13-1
address-range size, 13-9
base address, 13-9
conditions after reset, 13-11
example, 13-9, 13-12
initializing, 13-11, 13-17
overlapping ranges, 13-9, 13-11
overview, 2-6
registers, 13-11–13-12
base address, 13-9
conditions after reset, 13-11
example, 13-9, 13-12
initializing, 13-11, 13-17
overlapping ranges, 13-9, 13-11
overview, 2-6
registers, 13-11–13-12
Clear, defined, 1-3
CLKOUT, 12-1, 13-3, 13-18, 13-22, B-7
CLKOUT, 12-1, 13-3, 13-18, 13-22, B-7
and HOLD#, 13-30
and internal timing, 2-8
and interrupts, 6-6
and READY, 13-27
considerations, 7-10
reset status, 7-4
and internal timing, 2-8
and interrupts, 6-6
and READY, 13-27
considerations, 7-10
reset status, 7-4
Clock
external, 11-7
generator, 11-7
internal, and idle mode, 12-5, 12-6, 12-7
modes (80C196NU), 12-13
phases, internal, 2-9
slow, 10-6
generator, 11-7
internal, and idle mode, 12-5, 12-6, 12-7
modes (80C196NU), 12-13
phases, internal, 2-9
slow, 10-6
CLR instruction, A-2, A-11, A-47, A-53, A-60
CLRB instruction, A-2, A-11, A-47, A-53, A-60
CLRC instruction, A-3, A-11, A-52, A-59, A-67
CLRVT instruction, A-3, A-11, A-52, A-59, A-67
CLRB instruction, A-2, A-11, A-47, A-53, A-60
CLRC instruction, A-3, A-11, A-52, A-59, A-67
CLRVT instruction, A-3, A-11, A-52, A-59, A-67