Intel 80C196NU ユーザーズマニュアル
8XC196NP, 80C196NU USER’S MANUAL
Index-4
resetting the timers, 10-21, C-22
selecting the capture/compare event, 10-20,
selecting the capture/compare event, 10-20,
C-21
selecting the time base, 10-19, C-20
selecting up or down counting, 10-16, 10-17,
selecting up or down counting, 10-16, 10-17,
C-46, C-47
signals, 10-2
using for PWM, 6-26, 6-32
See also port 1, port 6, PWM, timer/counters
using for PWM, 6-26, 6-32
See also port 1, port 6, PWM, timer/counters
EPA0_CON, C-50, C-53
EPA0_TIME, C-50, C-53
EPA1_CON, 10-19, C-20, C-50, C-53
EPA1_TIME, C-50, C-53
EPA2_CON, C-50, C-53
EPA2_TIME, C-50, C-53
EPA3:0, B-8
EPA3_CON, 10-19, C-20, C-50, C-53
EPA3_TIME, C-50, C-53
EPA_MASK, C-50, C-53
EPA_PEND, C-50, C-53
EPAx_CON, 10-3
EPA0_TIME, C-50, C-53
EPA1_CON, 10-19, C-20, C-50, C-53
EPA1_TIME, C-50, C-53
EPA2_CON, C-50, C-53
EPA2_TIME, C-50, C-53
EPA3:0, B-8
EPA3_CON, 10-19, C-20, C-50, C-53
EPA3_TIME, C-50, C-53
EPA_MASK, C-50, C-53
EPA_PEND, C-50, C-53
EPAx_CON, 10-3
settings and operations, 10-18
EPAx_TIME, 10-3
EPC, 2-6, 5-23, 5-25, 7-13
EPORT, 2-6, 2-11, 5-1, 5-23, 7-11
EPC, 2-6, 5-23, 5-25, 7-13
EPORT, 2-6, 2-11, 5-1, 5-23, 7-11
and external address, 13-1
block diagram, 7-13
complementary output mode, 7-14
configuration register settings, 7-17
configuring pins, 7-17
block diagram, 7-13
complementary output mode, 7-14
configuration register settings, 7-17
configuring pins, 7-17
for extended address, 7-17
for I/O, 7-17
for I/O, 7-17
considerations, 7-18, 7-19
input buffers, 7-19
input mode, 7-16
logic tables, 7-16
open-drain output mode, 7-14
operation, 7-12
output enable, 7-14
overview, 7-1
pins, 7-11
reset, 7-14
SFRs, 7-12
structure, 7-15
input buffers, 7-19
input mode, 7-16
logic tables, 7-16
open-drain output mode, 7-14
operation, 7-12
output enable, 7-14
overview, 7-1
pins, 7-11
reset, 7-14
SFRs, 7-12
structure, 7-15
EPORT.3:0, B-8
EPTS instruction, 6-10, A-3, A-18, A-52, A-59,
EPTS instruction, 6-10, A-3, A-18, A-52, A-59,
A-67
ESD protection, 7-4, 7-14, 11-5
EST instruction, 4-6, A-3, A-19, A-47, A-56, A-63
ESTB instruction, 4-6, A-3, A-19, A-47, A-56,
ESTB instruction, 4-6, A-3, A-19, A-47, A-56,
A-63
Event, 10-1
Event processor array‚ See EPA
EXT instruction, A-2, A-19, A-47, A-53, A-60
EXTB instruction, A-2, A-20, A-47, A-53, A-60
Extended address lines, 5-1
Extended addressing, 2-4, 2-11, 4-11, 5-1, 5-23
Event processor array‚ See EPA
EXT instruction, A-2, A-19, A-47, A-53, A-60
EXTB instruction, A-2, A-20, A-47, A-53, A-60
Extended address lines, 5-1
Extended addressing, 2-4, 2-11, 4-11, 5-1, 5-23
code execution, 4-5
instructions, 4-5, 4-6, 5-24
port‚ See EPORT
program counter, 2-6
instructions, 4-5, 4-6, 5-24
port‚ See EPORT
program counter, 2-6
External memory, 5-2
fetching code, 5-25
flash, example in 1-Mbyte mode, 5-31
RAM, example in 1-Mbyte mode, 5-31
RAM, example in 64-Kbyte mode, 5-27, 5-29
flash, example in 1-Mbyte mode, 5-31
RAM, example in 1-Mbyte mode, 5-31
RAM, example in 64-Kbyte mode, 5-27, 5-29
EXTINT, 6-3
and idle mode, 12-6
and powerdown mode, 12-6, 12-8
hardware considerations, 12-9
and powerdown mode, 12-6, 12-8
hardware considerations, 12-9
EXTINT3:0, B-8
EXTINTx, 12-1
EXTINTx, 12-1
F
f, defined, 1-3
FaxBack service, 1-8
FE opcode
FaxBack service, 1-8
FE opcode
and inhibiting interrupts, 6-7
Flash memory, See external memory, flash
Floating point library, 4-5
Formulas
Floating point library, 4-5
Formulas
capacitor size (powerdown circuit), 12-11
clock period (t), 2-9
PH1 and PH2 frequency, 2-9
PWM duty cycle, 6-26
PWM frequency, 6-26
state time, 2-9
clock period (t), 2-9
PH1 and PH2 frequency, 2-9
PWM duty cycle, 6-26
PWM frequency, 6-26
state time, 2-9
FPAL-96, 4-5
Frequency (f), 2-9
F
Frequency (f), 2-9
F
XTAL
1
, 2-9
H
Handbooks, ordering, 1-6
Hardware
Hardware
addressing modes, 4-6