Analog Devices AD5560 Evaluation Board EVAL-AD5560EBUZ マニュアル

目次

• Features

  1
• Applications

  1
• General Description

  1
• Revision History

  3
• Functional Block Diagram

  4
• Specifications

  5
  • Timing Characteristics

    13
  • Timing Diagrams

    13
• Absolute Maximum Ratings

  15
  • ESD Caution

    15
• Pin Configurations and Function Descriptions

  16
• Typical Performance Characteristics

  20
• Terminology

  28
• Theory of Operation

  29
  • Force Amplifier

    29
    • HW_INH Function

      29
  • DAC Reference Voltage (VREF)

    29
  • Open-Sense Detect (OSD) Alarm and Clamp

    29
  • Device Under Test Ground (DUTGND)

    29
    • DUTGND Kelvin Sense

      29
    • Kelvin Alarm (KELALM)

      29
  • GPO

    30
  • Comparators

    30
  • Current Clamps

    30
    • Clamp Alarm Function (CLALM)

      30
    • Clamp Enable Function (CLEN/LOAD)

      30
  • Short-Circuit Protection

    30
  • Guard Amplifier

    30
  • Compensation Capacitors

    30
  • Current Range Selection

    31
  • High Current Ranges

    31
    • Master and Slaves in Force Voltage (FV) Mode

      31
    • Master in FV Mode, Slaves in Force Current (FI) Mode

      32
  • Ideal Sequence for Gang Mode

    32
  • Compensation for Gang Mode

    32
  • System Force/Sense Switches

    32
  • Die Temperature Sensor and Thermal Shutdown

    33
  • Measure Output (MEASOUT)

    33
  • VMID Voltage

    33
  • Force Amplifier Stability

    36
    • Safe Mode

      36
    • Autocompensation Mode

      36
    • Manual Compensation Mode

      36
  • Poles and Zeros in a Typical System

    37
  • Minimizing the Number of External Compensation Components

    37
    • CFx Pins

      37
    • CCx Pins

      37
  • Extra Poles and Zeros in the AD5560

    37
    • The Effect of CCx

      37
    • The Effect of CFx

      37
    • The Effect of RZ

      37
    • The Effect of RP

      37
  • Compensation Strategies

    38
    • Ensuring Stability into an Unknown Capacitor Up to a Maximum Value

      38
  • Optimizing Performance for a Known Capacitor Using Autocompensation Mode

    38
  • Adjusting the Autocompensation Mode

    39
  • Dealing with Parallel Load Capacitors

    39
  • DAC Levels

    39
  • Force and Comparator DACs

    39
  • Clamp DACs

    39
  • OSD DAC

    40
  • DUTGND DAC

    40
  • Offset DAC

    40
  • Offset and Gain Registers

    40
    • Offset and Gain Registers for the Force Amplifier DAC

      40
    • Offset and Gain Registers for the Comparator DACs

      40
    • Offset and Gain Registers for the Clamp DACs

      40
  • Reference Selection

    41
  • Choosing AVDD/AVSS Power Supply Rails

    41
  • Choosing HCAVSSx and HCAVDDx Supply Rails

    41
  • Power Dissipation

    41
  • Package Composition and Maximum Vertical Force

    42
  • Slew Rate Control

    42
    • Programmable Slew Rate

      42
    • Ramp Function

      42
• Serial Interface

  44
  • SPI Interface

    44
  • SPI Write Mode

    44
  • SDO Output

    44
  • RESET Function

    44
  • BUSY Function

    44
  • LOAD Function

    44
  • Register Update Rates

    45
• Control Registers

  46
  • DPS and DAC Addressing

    46
  • Readback Mode

    57
  • DAC Readback

    57
  • Power-On Default

    57
  • Using the HCAVDDx and HCAVSSx Supplies

    59
  • Power Supply Sequencing

    59
  • Required External Components

    60
  • Power Supply Decoupling

    61
• Applications Information

  62
  • Thermal Considerations

    62
  • Temperature Contour Map on the Top of the Package

    63
    • TQFP_EP Package

      63
    • BGA Package

      63
• Outline Dimensions

  64
  • Ordering Guide

    65