ユーザーズマニュアル目次Title Page2Copyright Page3Contents4CHAPTER 1 Introduction201.3 Electronic Support Systems231.3.1 FaxBack Service231.3.2 Bulletin Board System (BBS)241.3.2.1 How to Find ApBUILDER Software and Hyperte...251.3.3 CompuServe Forums251.3.4 World Wide Web251.4 Technical Support251.5 Product Literature261.6 Training Classes261.1 How to Use This Manual211.2 Related Documents22CHAPTER 2 Overview of the 80C186 Family Architectu...302.1 Architectural Overview302.1.1 Execution Unit312.1.2 Bus Interface Unit322.1.3 General Registers332.1.4 Segment Registers342.1.5 Instruction Pointer352.1.6 Flags362.1.7 Memory Segmentation372.1.8 Logical Addresses392.1.9 Dynamically Relocatable Code422.1.10 Stack Implementation442.1.11 Reserved Memory and I/O Space442.2 Software Overview462.2.1 Instruction Set462.2.1.1 Data Transfer Instructions472.2.1.2 Arithmetic Instructions482.2.1.3 Bit Manipulation Instructions502.2.1.4 String Instructions512.2.1.5 Program Transfer Instructions522.2.1.6 Processor Control Instructions562.2.2 Addressing Modes562.2.2.1 Register and Immediate Operand Addressing ...562.2.2.2 Memory Addressing Modes572.2.2.3 I/O Port Addressing652.2.2.4 Data Types Used in the 80C186 Modular Core...662.3 Interrupts and Exception Handling682.3.1 Interrupt/Exception Processing682.3.1.1 Non-Maskable Interrupts712.3.1.2 Maskable Interrupts722.3.1.3 Exceptions722.3.2 Software Interrupts742.3.3 Interrupt Latency742.3.4 Interrupt Response Time752.3.5 Interrupt and Exception Priority75CHAPTER 3 Bus Interface Unit823.1 Multiplexed Address and Data Bus823.2 Address and Data Bus Concepts823.2.1 16-Bit Data Bus823.2.2 8-Bit Data Bus863.3 Memory and I/O Interfaces873.3.1 16-Bit Bus Memory and I/O Requirements883.3.2 8-Bit Bus Memory and I/O Requirements883.4 Bus Cycle Operation883.4.1 Address/Status Phase913.4.2 Data Phase943.4.3 Wait States943.4.4 Idle States993.5 Bus Cycles1013.5.1 Read Bus Cycles1013.5.1.1 Refresh Bus Cycles1033.5.2 Write Bus Cycles1033.5.3 Interrupt Acknowledge Bus Cycle1063.5.3.1 System Design Considerations1083.5.4 HALT Bus Cycle1093.5.5 Temporarily Exiting the HALT Bus State1113.5.6 Exiting HALT1133.6 System Design Alternatives1143.6.1 Buffering the Data Bus1153.6.2 Synchronizing Software and Hardware Events1173.6.3 Using a Locked Bus1183.6.4 Using the Queue Status Signals1193.7 Multi-master Bus System Designs1203.7.1 Entering Bus HOLD1203.7.1.1 HOLD Bus Latency1213.7.1.2 Refresh Operation During a Bus HOLD1223.7.2 Exiting HOLD1243.8 Bus Cycle Priorities125CHAPTER 4 Peripheral Control Block1304.1 Peripheral Control Registers1304.2 PCB Relocation Register1304.3 Reserved Locations1334.4 Accessing the Peripheral Control Block1334.4.1 Bus Cycles1334.4.2 READY Signals and Wait States1334.4.3 F-Bus Operation1344.4.3.1 Writing the PCB Relocation Register1354.4.3.2 Accessing the Peripheral Control Registers...1354.4.3.3 Accessing Reserved Locations1354.5 Setting the PCB Base Location1354.5.1 Considerations for the 80C187 Math Coprocess...136CHAPTER 5 Clock Generation and Power Management1405.1 Clock Generation1405.1.1 Crystal Oscillator1405.1.1.1 Oscillator Operation1415.1.1.2 Selecting Crystals1445.1.2 Using an External Oscillator1455.1.3 Output from the Clock Generator1455.1.4 Reset and Clock Synchronization1455.2 Power Management1495.2.1 Power-Save Mode1505.2.1.1 Entering Power-Save Mode1505.2.1.2 Leaving Power-Save Mode1525.2.1.3 Example Power-Save Initialization Code152Example 51. Initializing the Power Management Uni...153CHAPTER 6 Chip-Select Unit1566.1 Common Methods for Generating Chip-Selects1566.2 Chip-Select Unit Features and Benefits1566.3 Chip-Select Unit Functional Overview1576.4 Programming1616.4.1 Initialization Sequence1616.4.2 Programming the Active Ranges1676.4.2.1 UCS Active Range1676.4.2.2 LCS Active Range1686.4.2.3 MCS Active Range1686.4.2.4 PCS Active Range1706.4.3 Bus Wait State and Ready Control1706.4.4 Overlapping Chip-Selects1716.4.5 Memory or I/O Bus Cycle Decoding1726.4.6 Programming Considerations1726.5 Chip-Selects And Bus Hold1736.6 Examples1736.6.1 Example 1: Typical System Configuration173Example 61. Initializing the Chip-Select Unit175CHAPTER 7 Refresh Control Unit1807.1 The Role of the Refresh Control Unit1817.2 Refresh Control Unit Capabilities1817.3 Refresh Control Unit Operation1817.4 Refresh Addresses1837.5 Refresh Bus Cycles1847.6 Guidelines for Designing DRAM Controllers1847.7 Programming the Refresh Control Unit1867.7.1 Calculating the Refresh Interval1867.7.2 Refresh Control Unit Registers1867.7.2.1 Refresh Base Address Register1877.7.2.2 Refresh Clock Interval Register1877.7.2.3 Refresh Control Register1887.7.3 Programming Example189Example 71. Initializing the Refresh Control Unit...1907.8 Refresh Operation and Bus HOLD191CHAPTER 8 Interrupt Control Unit1968.1 Functional Overview1968.2 Master Mode1978.2.1 Generic Functions in Master Mode1978.2.1.1 Interrupt Masking1988.2.1.2 Interrupt Priority1988.2.1.3 Interrupt Nesting1998.3 Functional Operation In Master Mode2008.3.1 Typical Interrupt Sequence2008.3.2 Priority Resolution2008.3.2.1 Priority Resolution Example2018.3.2.2 Interrupts That Share a Single Source2028.3.3 Cascading with External 8259As2028.3.3.1 Special Fully Nested Mode2038.3.4 Interrupt Acknowledge Sequence2048.3.5 Polling2048.3.6 Edge and Level Triggering2058.3.7 Additional Latency and Response Time2058.4 Programming the Interrupt Control Unit2068.4.1 Interrupt Control Registers2078.4.2 Interrupt Request Register2118.4.3 Interrupt Mask Register2118.4.4 Priority Mask Register2128.4.5 In-Service Register2138.4.6 Poll and Poll Status Registers2148.4.7 End-of-Interrupt (EOI) Register2168.4.8 Interrupt Status Register2178.5 Slave Mode2188.5.1 Slave Mode Programming2208.5.1.1 Interrupt Vector Register2218.5.1.2 End-Of-Interrupt Register2228.5.1.3 Other Registers2238.5.2 Interrupt Vectoring in Slave Mode2248.5.3 Initializing the Interrupt Control Unit for ...225Example 81. Initializing the Interrupt Control Un...226CHAPTER 9 Timer/Counter Unit2309.1 Functional Overview2309.2 Programming the Timer/Counter Unit2359.2.1 Initialization Sequence2409.2.2 Clock Sources2419.2.3 Counting Modes2419.2.3.1 Retriggering2429.2.4 Pulsed and Variable Duty Cycle Output2439.2.5 Enabling/Disabling Counters2449.2.6 Timer Interrupts2459.2.7 Programming Considerations2459.3 Timing2459.3.1 Input Setup and Hold Timings2459.3.2 Synchronization and Maximum Frequency2469.3.2.1 Timer/Counter Unit Application Examples2469.3.3 Real-Time Clock2469.3.4 Square-Wave Generator2469.3.5 Digital One-Shot246Example 91. Configuring a Real-Time Clock247Example 92. Configuring a Square-Wave Generator250Example 93. Configuring a Digital One-Shot251CHAPTER 10 Direct Memory Access Unit25610.1 Functional Overview25610.1.1 The DMA Transfer25610.1.1.1 DMA Transfer Directions25810.1.1.2 Byte and Word Transfers25810.1.2 Source and Destination Pointers25810.1.3 DMA Requests25810.1.4 External Requests25910.1.4.1 Source Synchronization26010.1.4.2 Destination Synchronization26010.1.5 Internal Requests26110.1.5.2 Unsynchronized Transfers26110.1.6 DMA Transfer Counts26210.1.7 Termination and Suspension of DMA Transfers...26210.1.7.1 Termination at Terminal Count26210.1.7.2 Software Termination26210.1.7.3 Suspension of DMA During NMI26210.1.7.4 Software Suspension26210.1.8 DMA Unit Interrupts26310.1.9 DMA Cycles and the BIU26310.1.10 The Two-Channel DMA Unit26310.1.10.1 DMA Channel Arbitration26310.1.10.1.1 Fixed Priority26310.1.10.1.2 Rotating Priority26510.2 Programming the DMA Unit26510.2.1 DMA Channel Parameters26510.2.1.1 Programming the Source and Destination Po...26510.2.1.2 Selecting Byte or Word Size Transfers26910.2.1.3 Selecting the Source of DMA Requests27210.2.1.4 Arming the DMA Channel27310.2.1.5 Selecting Channel Synchronization27310.2.1.6 Programming the Transfer Count Options27310.2.1.7 Generating Interrupts on Terminal Count27410.2.1.8 Setting the Relative Priority of a Channe...27410.2.2 Suspension of DMA Transfers27510.2.3 Initializing the DMA Unit27510.3 Hardware Considerations and the Dma Unit27510.3.1 DRQ Pin Timing Requirements27510.3.2 DMA Latency27610.3.3 DMA Transfer Rates27610.3.4 Generating a DMA Acknowledge27710.4 DMA Unit Examples277Example 101. Initializing the DMA Unit278Example 102. Timed DMA Transfers281CHAPTER 11 Math Coprocessing28611.1 Overview of Math Coprocessing28611.2 Availability of Math Coprocessing28611.3 The 80c187 Math Coprocessor28711.3.1 80C187 Instruction Set28711.3.1.1 Data Transfer Instructions28811.3.1.2 Arithmetic Instructions28811.3.1.3 Comparison Instructions29011.3.1.4 Transcendental Instructions29011.3.1.5 Constant Instructions29111.3.1.6 Processor Control Instructions29111.3.2 80C187 Data Types29211.4 Microprocessor and Coprocessor Operation29211.4.1 Clocking the 80C18729511.4.2 Processor Bus Cycles Accessing the 80C18729511.4.3 System Design Tips29611.4.4 Exception Trapping29811.5 Example Math Coprocessor Routines298Example 111. Initialization Sequence for 80C187 M...300Example 112. Floating Point Math Routine Using FS...301CHAPTER 12 Once Mode30412.1 Entering/Leaving Once Mode304APPENDIX A 80C186 Instruction Set Additions and Ex...308A.1 80C186 Instruction Set Additions308A.1.1 Data Transfer Instructions308A.1.2 String Instructions309A.1.3 High-Level Instructions309A.2 80C186 Instruction Set Enhancements315A.2.1 Data Transfer Instructions315A.2.2 Arithmetic Instructions316A.2.3 Bit Manipulation Instructions316A.2.3.1 Shift Instructions316A.2.3.2 Rotate Instructions317APPENDIX B Input Synchronization320B.1 Why Synchronizers are Required320B.2 Asynchronous Pins321APPENDIX C Instruction Set Descriptions324APPENDIX D Instruction Set Opcodes and Clock Cycle...374Figures31Figure 21. Simplified Functional Block Diagram of...31Figure 22. Physical Address Generation32Figure 23. General Registers33Figure 24. Segment Registers35Figure 25. Processor Status Word38Figure 26. Segment Locations in Physical Memory39Figure 27. Currently Addressable Segments40Figure 28. Logical and Physical Address41Figure 29. Dynamic Code Relocation43Figure 210. Stack Operation45Figure 211. Flag Storage Format48Figure 212. Memory Address Computation58Figure 213. Direct Addressing59Figure 214. Register Indirect Addressing60Figure 215. Based Addressing60Figure 216. Accessing a Structure with Based Addr...61Figure 217. Indexed Addressing62Figure 218. Accessing an Array with Indexed Addre...62Figure 219. Based Index Addressing63Figure 220. Accessing a Stacked Array with Based ...64Figure 221. String Operand65Figure 222. I/O Port Addressing65Figure 223. 80C186 Modular Core Family Supported ...67Figure 224. Interrupt Control Unit68Figure 225. Interrupt Vector Table69Figure 226. Interrupt Sequence71Figure 227. Interrupt Response Factors75Figure 228. Simultaneous NMI and Exception76Figure 229. Simultaneous NMI and Single Step Inte...77Figure 230. Simultaneous NMI, Single Step and Mas...78Figure 31. Physical Data Bus Models83Figure 32. 16-Bit Data Bus Byte Transfers84Figure 33. 16-Bit Data Bus Even Word Transfers85Figure 34. 16-Bit Data Bus Odd Word Transfers86Figure 35. 8-Bit Data Bus Word Transfers87Figure 36. Typical Bus Cycle89Figure 37. T-State Relation to CLKOUT89Figure 38. BIU State Diagram90Figure 39. T-State and Bus Phases91Figure 310. Address/Status Phase Signal Relations...92Figure 311. Demultiplexing Address Information93Figure 312. Data Phase Signal Relationships95Figure 313. Typical Bus Cycle with Wait States96Figure 314. ARDY and SRDY Pin Block Diagram96Figure 315. Generating a Normally Not-Ready Bus S...97Figure 316. Generating a Normally Ready Bus Signa...98Figure 317. Normally Not-Ready System Timing99Figure 318. Normally Ready System Timings100Figure 319. Typical Read Bus Cycle102Figure 320. Read-Only Device Interface103Figure 321. Typical Write Bus Cycle104Figure 322. 16-Bit Bus Read/Write Device Interfac...105Figure 323. Interrupt Acknowledge Bus Cycle107Figure 324. Typical 82C59A Interface108Figure 325. HALT Bus Cycle110Figure 326. Returning to HALT After a HOLD/HLDA B...111Figure 327. Returning to HALT After a Refresh Bus...112Figure 328. Returning to HALT After a DMA Bus Cyc...113Figure 329. Exiting HALT114Figure 330. DEN and DT/R Timing Relationships115Figure 331. Buffered AD Bus System116Figure 332. Qualifying DEN with Chip-Selects117Figure 333. Queue Status Timing120Figure 334. Timing Sequence Entering HOLD121Figure 335. Refresh Request During HOLD123Figure 336. Latching HLDA124Figure 337. Exiting HOLD125Figure 41. PCB Relocation Register131Figure 51. Clock Generator140Figure 52. Ideal Operation of Pierce Oscillator141Figure 53. Crystal Connections to Microprocessor142Figure 54. Equations for Crystal Calculations143Figure 55. Simple RC Circuit for Powerup Reset146Figure 56. Cold Reset Waveform147Figure 57. Warm Reset Waveform148Figure 58. Clock Synchronization at Reset149Figure 59. Power-Save Register151Figure 510. Power-Save Clock Transition152Figure 61. Common Chip-Select Generation Methods157Figure 62. Chip-Select Block Diagram158Figure 63. Chip-Select Relative Timings159Figure 64. UCS Reset Configuration160Figure 65. UMCS Register Definition162Figure 66. LMCS Register Definition163Figure 67. MMCS Register Definition164Figure 68. PACS Register Definition165Figure 69. MPCS Register Definition166Figure 610. MCS3:0 Active Ranges169Figure 611. Wait State and Ready Control Function...171Figure 612. Using Chip-Selects During HOLD173Figure 613. Typical System174Figure 71. Refresh Control Unit Block Diagram180Figure 72. Refresh Control Unit Operation Flow Ch...182Figure 73. Refresh Address Formation183Figure 74. Suggested DRAM Control Signal Timing R...185Figure 75. Formula for Calculating Refresh Interv...186Figure 76. Refresh Base Address Register187Figure 77. Refresh Clock Interval Register188Figure 78. Refresh Control Register189Figure 79. Regaining Bus Control to Run a DRAM Re...192Figure 81. Interrupt Control Unit in Master Mode197Figure 82. Using External 8259A Modules in Cascad...203Figure 83. Interrupt Control Unit Latency and Res...206Figure 84. Interrupt Control Register for Interna...208Figure 85. Interrupt Control Register for Noncasc...209Figure 86. Interrupt Control Register for Cascada...210Figure 87. Interrupt Request Register211Figure 88. Interrupt Mask Register212Figure 89. Priority Mask Register213Figure 810. In-Service Register214Figure 811. Poll Register215Figure 812. Poll Status Register216Figure 813. End-of-Interrupt Register217Figure 814. Interrupt Status Register218Figure 815. Interrupt Control Unit in Slave Mode219Figure 816. Interrupt Sources in Slave Mode220Figure 817. Interrupt Vector Register (Slave Mode...222Figure 818. End-of-Interrupt Register in Slave Mo...223Figure 819. Request, Mask, and In-Service Registe...223Figure 820. Interrupt Vectoring in Slave Mode224Figure 821. Interrupt Response Time in Slave Mode...225Figure 91. Timer/Counter Unit Block Diagram231Figure 92. Counter Element Multiplexing and Timer...232Figure 93. Timers 0 and 1 Flow Chart233Figure 93. Timers 0 and 1 Flow Chart (Continued)234Figure 94. Timer/Counter Unit Output Modes235Figure 95. Timer 0 and Timer 1 Control Registers236Figure 95. Timer 0 and Timer 1 Control Registers ...237Figure 96. Timer 2 Control Register238Figure 97. Timer Count Registers239Figure 98. Timer Maxcount Compare Registers240Figure 99. TxOUT Signal Timing244Figure 101. Typical DMA Transfer257Figure 102. DMA Request Minimum Response Time259Figure 103. Source-Synchronized Transfers260Figure 104. Destination-Synchronized Transfers261Figure 105. Two-Channel DMA Module264Figure 106. Examples of DMA Priority265Figure 107. DMA Source Pointer (High-Order Bits)266Figure 108. DMA Source Pointer (Low-Order Bits)267Figure 109. DMA Destination Pointer (High-Order B...268Figure 1010. DMA Destination Pointer (Low-Order B...269Figure 1011. DMA Control Register270Figure 1011. DMA Control Register (Continued)271Figure 1011. DMA Control Register (Continued)272Figure 1012. Transfer Count Register274Table 116. 80C187 Processor Control Instructions ...291Figure 111. 80C187-Supported Data Types293Figure 112. 80C186 Modular Core Family/80C187 Sys...294Figure 113. 80C187 Configuration with a Partially...297Figure 114. 80C187 Exception Trapping via Process...299Figure 121. Entering/Leaving ONCE Mode305Figure A1. Formal Definition of ENTER310Figure A2. Variable Access in Nested Procedures311Figure A3. Stack Frame for Main at Level 1311Figure A4. Stack Frame for Procedure A at Level 2...312Figure A5. Stack Frame for Procedure B at Level 3...313Figure A6. Stack Frame for Procedure C at Level 3...314Figure B1. Input Synchronization Circuit320Tables21Table 11. Comparison of 80C186 Modular Core Famil...21Table 12. Related Documents and Software(Continu...22Table 21. Implicit Use of General Registers34Table 22. Logical Address Sources 42Table 23. Data Transfer Instructions 47Table 24. Arithmetic Instructions 49Table 25. Arithmetic Interpretation of 8-Bit Numb...50Table 26. Bit Manipulation Instructions 50Table 27. String Instructions 51Table 28. String Instruction Register and Flag Us...52Table 29. Program Transfer Instructions 54Table 210. Interpretation of Conditional Transfer...55Table 211. Processor Control Instructions56Table 212. Supported Data Types 66Table 31. Bus Cycle Types 93Table 32. Read Bus Cycle Types 101Table 33. Read Cycle Critical Timing Parameters ...101Table 34. Write Bus Cycle Types104Table 35. Write Cycle Critical Timing Parameters ...106Table 36. HALT Bus Cycle Pin States110Table 37. Queue Status Signal Decoding119Table 38. Signal Condition Entering HOLD 121Table 41. Peripheral Control Block132Table 51. Suggested Values for Inductor L1 in Thi...143Table 61. Chip-Select Unit Registers 161Table 62. UCS Block Size and Starting Address167Table 6 3. LCS Active Range168Table 64. MCS Active Range168Table 65. MCS Block Size and Start Address Restri...169Table 66. PCS Active Range170Table 71. Identification of Refresh Bus Cycles 184Table 81. Default Interrupt Priorities 198Table 82. Fixed Interrupt Types204Table 83. Interrupt Control Unit Registers in Mas...206Table 84. Interrupt Control Unit Register Compari...221Table 85. Slave Mode Fixed Interrupt Type Bits221Table 91. Timer 0 and 1 Clock Sources241Table 92. Timer Retriggering243Table 111. 80C187 Data Transfer Instructions288Table 112. 80C187 Arithmetic Instructions 289Table 113. 80C187 Comparison Instructions 290Table 114. 80C187 Transcendental Instructions 290Table 115. 80C187 Constant Instructions291Table 117. 80C187 I/O Port Assignments295Table C1. Instruction Format Variables324Table C2. Instruction Operands325Table C3. Flag Bit Functions326Table C4. Instruction Set (Continued)327Table D1. Operand Variables374Table D2. Instruction Set Summary (Continued)375Table D3. Machine Instruction Decoding Guide (Con...382Table D4. Mnemonic Encoding Matrix (Left Half)393Table D4. Mnemonic Encoding Matrix (Right Half)394Table D5. Abbreviations for Mnemonic Encoding Mat...395サイズ： 1.92MBページ数： 405Language: Englishマニュアルを開く
