Intel Celeron 440 マニュアル

目次

• Contents

  3
  • Figures

    5
  • Tables

    5
• Revision History

  7
• Intel® Celeron® Processor 400 Series Features

  8
• Intel® Celeron® Processor 400D Series

  1
• 1 Introduction

  9
  • 1.1 Terminology

    9
    • 1.1.1 Processor Packaging Terminology

      10
  • 1.2 References

    11
• 2 Electrical Specifications

  13
  • 2.1 Power and Ground Lands

    13
  • 2.2 Decoupling Guidelines

    13
    • 2.2.1 Vcc Decoupling

      13
    • 2.2.2 Vtt Decoupling

      13
    • 2.2.3 FSB Decoupling

      14
  • 2.3 Voltage Identification

    14
  • 2.4 Market Segment Identification (MSID)

    16
  • 2.5 Reserved, Unused and TESTHI Signals

    16
  • 2.6 Voltage and Current Specification

    17
    • 2.6.1 Absolute Maximum and Minimum Ratings

      17
    • 2.6.2 DC Voltage and Current Specification

      19
    • 2.6.3 Vcc Overshoot

      21
    • 2.6.4 Die Voltage Validation

      22
  • 2.7 Signaling Specifications

    22
    • 2.7.1 FSB Signal Groups

      23
    • 2.7.2 CMOS and Open Drain Signals

      25
    • 2.7.3 Processor DC Specifications

      25
      • 2.7.3.1 GTL+ Front Side Bus Specifications

        27
  • 2.8 Clock Specifications

    28
    • 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

      28
    • 2.8.2 FSB Frequency Select Signals (BSEL[2:0])

      29
    • 2.8.3 Phase Lock Loop (PLL) and Filter

      29
    • 2.8.4 BCLK[1:0] Specifications (CK505 based Platforms)

      30
    • 2.8.5 BCLK[1:0] Specifications (CK410 based Platforms)

      32
  • 2.9 PECI DC Specifications

    34
• 3 Package Mechanical Specifications

  35
  • 3.1 Package Mechanical Drawing

    35
  • 3.2 Processor Component Keep-Out Zones

    39
  • 3.3 Package Loading Specifications

    39
  • 3.4 Package Handling Guidelines

    39
  • 3.5 Package Insertion Specifications

    40
  • 3.6 Processor Mass Specification

    40
  • 3.7 Processor Materials

    40
  • 3.8 Processor Markings

    40
  • 3.9 Processor Land Coordinates

    41
• 4 Land Listing and Signal Descriptions

  43
  • 4.1 Processor Land Assignments

    43
  • 4.2 Alphabetical Signals Reference

    66
• 5 Thermal Specifications and Design Considerations

  75
  • 5.1 Processor Thermal Specifications

    75
    • 5.1.1 Thermal Specifications

      75
    • 5.1.2 Thermal Metrology

      78
  • 5.2 Processor Thermal Features

    78
    • 5.2.1 Thermal Monitor

      78
    • 5.2.2 Thermal Monitor 2

      79
    • 5.2.3 On-Demand Mode

      80
    • 5.2.4 PROCHOT# Signal

      81
    • 5.2.5 THERMTRIP# Signal

      81
  • 5.3 Thermal Diode

    82
  • 5.4 Platform Environment Control Interface (PECI)

    84
    • 5.4.1 Introduction

      84
      • 5.4.1.1 Key Difference with Legacy Diode-Based Thermal Management

        84
    • 5.4.2 PECI Specifications

      86
      • 5.4.2.1 PECI Device Address

        86
      • 5.4.2.2 PECI Command Support

        86
      • 5.4.2.3 PECI Fault Handling Requirements

        86
      • 5.4.2.4 PECI GetTemp0() Error Code Support

        86
• 6 Features

  87
  • 6.1 Power-On Configuration Options

    87
  • 6.2 Clock Control and Low Power States

    87
    • 6.2.1 Normal State

      88
    • 6.2.2 HALT and Extended HALT Powerdown States

      88
      • 6.2.2.1 HALT Powerdown State

        88
      • 6.2.2.2 Extended HALT Powerdown State

        89
    • 6.2.3 Stop Grant State

      89
    • 6.2.4 HALT Snoop State and Stop Grant Snoop State

      90
• 7 Boxed Processor Specifications

  91
  • 7.1 Mechanical Specifications

    92
    • 7.1.1 Boxed Processor Cooling Solution Dimensions

      92
    • 7.1.2 Boxed Processor Fan Heatsink Weight

      94
    • 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly

      94
  • 7.2 Electrical Requirements

    94
    • 7.2.1 Fan Heatsink Power Supply

      94
  • 7.3 Thermal Specifications

    95
    • 7.3.1 Boxed Processor Cooling Requirements

      95
    • 7.3.2 Variable Speed Fan

      97
• 8 Debug Tools Specifications

  99
  • 8.1 Logic Analyzer Interface (LAI)

    99
    • 8.1.1 Mechanical Considerations

      99
    • 8.1.2 Electrical Considerations

      99