Intel E5-1428L マニュアル

目次

• Revision History

  3
• Contents

  4
  • Figures

    6
  • Tables

    7
• 1.0 Introduction

  8
  • 1.1 Electrical Datasheet Introduction

    8
    • 1.1.1 Structure and Scope

      9
    • 1.1.2 Related Publications

      9
    • 1.1.3 Terminology

      10
    • 1.1.4 State of Data

      13
• 2.0 Electrical Specifications

  14
  • 2.1 Integrated Voltage Regulation

    14
  • 2.2 Processor Signaling

    14
    • 2.2.1 System Memory Interface Signal Groups

      14
    • 2.2.2 PCI Express Signals

      14
    • 2.2.3 DMI2/PCI Express Signals

      15
    • 2.2.4 Intel® QuickPath Interconnect (Intel® QPI)

      15
    • 2.2.5 Platform Environmental Control Interface (PECI)

      15
    • 2.2.6 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN)

      16
    • 2.2.7 JTAG and Test Access Port (TAP) Signals

      16
    • 2.2.8 Processor Sideband Signals

      16
    • 2.2.9 Power, Ground and Sense Signals

      17
    • 2.2.10 Reserved or Unused Signals

      22
  • 2.3 Signal Group Summary

    22
  • 2.4 Power-On Configuration (POC) Options

    26
  • 2.5 Fault Resilient Booting (FRB)

    27
  • 2.6 Mixing Processors

    28
  • 2.7 Flexible Motherboard Guidelines (FMB)

    29
  • 2.8 Absolute Maximum and Minimum Ratings

    29
  • 2.9 DC Specifications

    31
    • 2.9.1 Voltage and Current Specifications

      31
    • 2.9.2 Die Voltage Validation

      35
    • 2.9.3 Signal DC Specifications

      36
      • 2.9.3.1 DDR4 Signal DC Specifications

        36
      • 2.9.3.2 PECI DC Specifications

        38
      • 2.9.3.3 System Reference Clock (BCLK{0/1}) DC Specifications

        38
      • 2.9.3.4 SMBus DC Specifications

        40
      • 2.9.3.5 JTAG and TAP Signals DC Specifications

        41
      • 2.9.3.6 Serial VID Interface (SVID) DC Specifications

        41
      • 2.9.3.7 Processor Asynchronous Sideband DC Specifications

        42
      • 2.9.3.8 Miscellaneous Signals DC Specifications

        42
  • 2.10 Package C-State Power Specifications

    42
  • 2.11 Signal Quality

    44
    • 2.11.1 DDR Signal Quality Specifications

      44
    • 2.11.2 I/O Signal Quality Specifications

      44
    • 2.11.3 Input Reference Clock Signal Quality Specifications

      44
    • 2.11.4 Overshoot/Undershoot Tolerance

      44
• 3.0 Processor Land Listing

  48
• 4.0 Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions

  49
  • 4.1 System Memory Interface

    49
  • 4.2 PCI Express* Based Interface Signals

    50
  • 4.3 DMI2/PCI Express Port 0 Signals

    52
  • 4.4 Intel® QuickPath Interconnect Signals

    52
  • 4.5 PECI Signal

    52
  • 4.6 System Reference Clock Signals

    52
  • 4.7 JTAG and TAP Signals

    53
  • 4.8 Serial VID Interface (SVID) Signals

    53
  • 4.9 Processor Asynchronous Sideband and Miscellaneous Signals

    53
  • 4.10 Processor Power and Ground Supplies

    57
• Appendix A: Pin List

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