Intel E5-1428L 사용자 매뉴얼

차례

• Revision History

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• Contents

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  • Figures

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  • Tables

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• 1.0 Introduction

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  • 1.1 Electrical Datasheet Introduction

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    • 1.1.1 Structure and Scope

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    • 1.1.2 Related Publications

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    • 1.1.3 Terminology

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    • 1.1.4 State of Data

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• 2.0 Electrical Specifications

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  • 2.1 Integrated Voltage Regulation

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  • 2.2 Processor Signaling

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    • 2.2.1 System Memory Interface Signal Groups

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    • 2.2.2 PCI Express Signals

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    • 2.2.3 DMI2/PCI Express Signals

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    • 2.2.4 Intel® QuickPath Interconnect (Intel® QPI)

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    • 2.2.5 Platform Environmental Control Interface (PECI)

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    • 2.2.6 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN)

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    • 2.2.7 JTAG and Test Access Port (TAP) Signals

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    • 2.2.8 Processor Sideband Signals

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    • 2.2.9 Power, Ground and Sense Signals

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    • 2.2.10 Reserved or Unused Signals

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  • 2.3 Signal Group Summary

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  • 2.4 Power-On Configuration (POC) Options

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  • 2.5 Fault Resilient Booting (FRB)

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  • 2.6 Mixing Processors

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  • 2.7 Flexible Motherboard Guidelines (FMB)

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  • 2.8 Absolute Maximum and Minimum Ratings

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  • 2.9 DC Specifications

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    • 2.9.1 Voltage and Current Specifications

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    • 2.9.2 Die Voltage Validation

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    • 2.9.3 Signal DC Specifications

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      • 2.9.3.1 DDR4 Signal DC Specifications

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      • 2.9.3.2 PECI DC Specifications

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      • 2.9.3.3 System Reference Clock (BCLK{0/1}) DC Specifications

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      • 2.9.3.4 SMBus DC Specifications

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      • 2.9.3.5 JTAG and TAP Signals DC Specifications

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      • 2.9.3.6 Serial VID Interface (SVID) DC Specifications

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      • 2.9.3.7 Processor Asynchronous Sideband DC Specifications

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      • 2.9.3.8 Miscellaneous Signals DC Specifications

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  • 2.10 Package C-State Power Specifications

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  • 2.11 Signal Quality

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    • 2.11.1 DDR Signal Quality Specifications

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    • 2.11.2 I/O Signal Quality Specifications

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    • 2.11.3 Input Reference Clock Signal Quality Specifications

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    • 2.11.4 Overshoot/Undershoot Tolerance

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• 3.0 Processor Land Listing

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• 4.0 Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions

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  • 4.1 System Memory Interface

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  • 4.2 PCI Express* Based Interface Signals

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  • 4.3 DMI2/PCI Express Port 0 Signals

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  • 4.4 Intel® QuickPath Interconnect Signals

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  • 4.5 PECI Signal

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  • 4.6 System Reference Clock Signals

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  • 4.7 JTAG and TAP Signals

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  • 4.8 Serial VID Interface (SVID) Signals

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  • 4.9 Processor Asynchronous Sideband and Miscellaneous Signals

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  • 4.10 Processor Power and Ground Supplies

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• Appendix A: Pin List

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