Intel i3-4360T マニュアル

目次

• Contents

  3
  • Figures

    6
  • Tables

    7
• Revision History

  9
• 1.0 Introduction

  10
  • 1.1 Supported Technologies

    11
  • 1.2 Interfaces

    12
  • 1.3 Power Management Support

    12
  • 1.4 Thermal Management Support

    13
  • 1.5 Package Support

    13
  • 1.6 Terminology

    13
  • 1.7 Related Documents

    16
• 2.0 Interfaces

  18
  • 2.1 System Memory Interface

    18
    • 2.1.1  System Memory Technology Supported

      19
    • 2.1.2 System Memory Timing Support

      20
    • 2.1.3 System Memory Organization Modes

      21
      • 2.1.3.1 System Memory Frequency

        22
      • 2.1.3.2  Intel® Fast Memory Access (Intel® FMA) Technology Enhancements

        22
      • 2.1.3.3  Data Scrambling

        23
  • 2.2 PCI Express* Interface

    23
    • 2.2.1 PCI Express* Support

      23
    • 2.2.2 PCI Express* Architecture

      24
    • 2.2.3 PCI Express* Configuration Mechanism

      24
  • 2.3 Direct Media Interface (DMI)

    26
  • 2.4 Processor Graphics

    28
  • 2.5 Processor Graphics Controller (GT)

    28
    • 2.5.1 3D and Video Engines for Graphics Processing

      29
    • 2.5.2 Multi Graphics Controllers Multi-Monitor Support

      31
  • 2.6 Digital Display Interface (DDI)

    31
  • 2.7 Intel® Flexible Display Interface (Intel® FDI)

    37
  • 2.8 Platform Environmental Control Interface (PECI)

    37
    • 2.8.1 PECI Bus Architecture

      37
• 3.0 Technologies

  39
  • 3.1 Intel® Virtualization Technology (Intel® VT)

    39
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    43
  • 3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)

    44
  • 3.4 Intel® Turbo Boost Technology 2.0

    45
  • 3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)

    45
  • 3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

    46
  • 3.7  Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)

    46
  • 3.8 Intel® 64 Architecture x2APIC

    47
  • 3.9  Power Aware Interrupt Routing (PAIR)

    48
  • 3.10 Execute Disable Bit

    48
  • 3.11  Supervisor Mode Execution Protection (SMEP)

    48
• 4.0 Power Management

  49
  • 4.1 Advanced Configuration and Power Interface (ACPI) States Supported

    50
  • 4.2 Processor Core Power Management

    51
    • 4.2.1 Enhanced Intel® SpeedStep® Technology Key Features

      51
    • 4.2.2 Low-Power Idle States

      52
    • 4.2.3 Requesting Low-Power Idle States

      53
    • 4.2.4 Core C-State Rules

      54
    • 4.2.5 Package C-States

      55
    • 4.2.6 Package C-States and Display Resolutions

      59
  • 4.3 Integrated Memory Controller (IMC) Power Management

    60
    • 4.3.1 Disabling Unused System Memory Outputs

      60
    • 4.3.2 DRAM Power Management and Initialization

      61
      • 4.3.2.1 Initialization Role of CKE

        62
      • 4.3.2.2 Conditional Self-Refresh

        62
      • 4.3.2.3 Dynamic Power-Down

        62
      • 4.3.2.4 DRAM I/O Power Management

        63
    • 4.3.3  DRAM Running Average Power Limitation (RAPL)

      63
    • 4.3.4 DDR Electrical Power Gating (EPG)

      63
  • 4.4 PCI Express* Power Management

    63
  • 4.5 Direct Media Interface (DMI) Power Management

    63
  • 4.6 Graphics Power Management

    64
    • 4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)

      64
    • 4.6.2 Graphics Render C-State

      64
    • 4.6.3 Intel® Graphics Dynamic Frequency

      64
• 5.0 Thermal Management

  65
  • 5.1 Desktop Processor Thermal Profiles

    67
    • 5.1.1 Processor (PCG 2013D and PCG 2014) Thermal Profile

      68
    • 5.1.2 Processor (PCG 2013C) Thermal Profile

      69
    • 5.1.3 Processor (PCG 2013B) Thermal Profile

      70
    • 5.1.4 Processor (PCG 2013A) Thermal Profile

      72
  • 5.2 Thermal Metrology

    73
  • 5.3 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1

    73
  • 5.4 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0

    75
  • 5.5 Thermal Specifications

    76
  • 5.6 Processor Temperature

    78
  • 5.7 Adaptive Thermal Monitor

    78
  • 5.8 THERMTRIP# Signal

    81
  • 5.9 Digital Thermal Sensor

    81
    • 5.9.1 Digital Thermal Sensor Accuracy (Taccuracy)

      82
  • 5.10 Intel® Turbo Boost Technology Thermal Considerations

    82
    • 5.10.1 Intel® Turbo Boost Technology Power Control and Reporting

      82
    • 5.10.2 Package Power Control

      83
    • 5.10.3 Turbo Time Parameter

      84
• 6.0 Signal Description

  86
  • 6.1 System Memory Interface Signals

    86
  • 6.2 Memory Reference Compensation Signals

    88
  • 6.3 Reset and Miscellaneous Signals

    89
  • 6.4 PCI Express* Interface Signals

    90
  • 6.5 Display Interface Signals

    90
  • 6.6 Direct Media Interface (DMI)

    90
  • 6.7 Phase Locked Loop (PLL) Signals

    91
  • 6.8 Testability Signals

    91
  • 6.9 Error and Thermal Protection Signals

    92
  • 6.10 Power Sequencing Signals

    92
  • 6.11 Processor Power Signals

    93
  • 6.12 Sense Signals

    93
  • 6.13 Ground and Non-Critical to Function (NCTF) Signals

    93
  • 6.14 Processor Internal Pull-Up / Pull-Down Terminations

    93
• 7.0 Electrical Specifications

  94
  • 7.1 Integrated Voltage Regulator

    94
  • 7.2 Power and Ground Lands

    94
  • 7.3 VCC Voltage Identification (VID)

    94
  • 7.4 Reserved or Unused Signals

    99
  • 7.5 Signal Groups

    99
  • 7.6 Test Access Port (TAP) Connection

    101
  • 7.7  DC Specifications

    101
  • 7.8 Voltage and Current Specifications

    102
    • 7.8.1 Platform Environment Control Interface (PECI) DC Characteristics

      107
    • 7.8.2 Input Device Hysteresis

      108
• 8.0 Package Mechanical Specifications

  109
  • 8.1 Processor Component Keep-Out Zone

    109
  • 8.2 Package Loading Specifications

    109
  • 8.3 Package Handling Guidelines

    110
  • 8.4 Package Insertion Specifications

    110
  • 8.5 Processor Mass Specification

    110
  • 8.6 Processor Materials

    110
  • 8.7 Processor Markings

    111
  • 8.8 Processor Land Coordinates

    111
  • 8.9 Processor Storage Specifications

    113
• 9.0 Processor Ball and Signal Information

  115