Manual Do Utilizador (CM8064601481958)índice analíticoContents3Figures6Tables7Revision History91.0 Introduction101.1 Supported Technologies111.2 Interfaces121.3 Power Management Support121.4 Thermal Management Support131.5 Package Support131.6 Terminology131.7 Related Documents162.0 Interfaces182.1 System Memory Interface182.1.1 System Memory Technology Supported192.1.2 System Memory Timing Support202.1.3 System Memory Organization Modes212.1.3.1 System Memory Frequency222.1.3.2 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements222.1.3.3 Data Scrambling232.2 PCI Express* Interface232.2.1 PCI Express* Support232.2.2 PCI Express* Architecture242.2.3 PCI Express* Configuration Mechanism242.3 Direct Media Interface (DMI)262.4 Processor Graphics282.5 Processor Graphics Controller (GT)282.5.1 3D and Video Engines for Graphics Processing292.5.2 Multi Graphics Controllers Multi-Monitor Support312.6 Digital Display Interface (DDI)312.7 Intel® Flexible Display Interface (Intel® FDI)372.8 Platform Environmental Control Interface (PECI)372.8.1 PECI Bus Architecture373.0 Technologies393.1 Intel® Virtualization Technology (Intel® VT)393.2 Intel® Trusted Execution Technology (Intel® TXT)433.3 Intel® Hyper-Threading Technology (Intel® HT Technology)443.4 Intel® Turbo Boost Technology 2.0453.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)453.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)463.7 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)463.8 Intel® 64 Architecture x2APIC473.9 Power Aware Interrupt Routing (PAIR)483.10 Execute Disable Bit483.11 Supervisor Mode Execution Protection (SMEP)484.0 Power Management494.1 Advanced Configuration and Power Interface (ACPI) States Supported504.2 Processor Core Power Management514.2.1 Enhanced Intel® SpeedStep® Technology Key Features514.2.2 Low-Power Idle States524.2.3 Requesting Low-Power Idle States534.2.4 Core C-State Rules544.2.5 Package C-States554.2.6 Package C-States and Display Resolutions594.3 Integrated Memory Controller (IMC) Power Management604.3.1 Disabling Unused System Memory Outputs604.3.2 DRAM Power Management and Initialization614.3.2.1 Initialization Role of CKE624.3.2.2 Conditional Self-Refresh624.3.2.3 Dynamic Power-Down624.3.2.4 DRAM I/O Power Management634.3.3 DRAM Running Average Power Limitation (RAPL)634.3.4 DDR Electrical Power Gating (EPG)634.4 PCI Express* Power Management634.5 Direct Media Interface (DMI) Power Management634.6 Graphics Power Management644.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)644.6.2 Graphics Render C-State644.6.3 Intel® Graphics Dynamic Frequency645.0 Thermal Management655.1 Desktop Processor Thermal Profiles675.1.1 Processor (PCG 2013D and PCG 2014) Thermal Profile685.1.2 Processor (PCG 2013C) Thermal Profile695.1.3 Processor (PCG 2013B) Thermal Profile705.1.4 Processor (PCG 2013A) Thermal Profile725.2 Thermal Metrology735.3 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1735.4 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0755.5 Thermal Specifications765.6 Processor Temperature785.7 Adaptive Thermal Monitor785.8 THERMTRIP# Signal815.9 Digital Thermal Sensor815.9.1 Digital Thermal Sensor Accuracy (Taccuracy)825.10 Intel® Turbo Boost Technology Thermal Considerations825.10.1 Intel® Turbo Boost Technology Power Control and Reporting825.10.2 Package Power Control835.10.3 Turbo Time Parameter846.0 Signal Description866.1 System Memory Interface Signals866.2 Memory Reference Compensation Signals886.3 Reset and Miscellaneous Signals896.4 PCI Express* Interface Signals906.5 Display Interface Signals906.6 Direct Media Interface (DMI)906.7 Phase Locked Loop (PLL) Signals916.8 Testability Signals916.9 Error and Thermal Protection Signals926.10 Power Sequencing Signals926.11 Processor Power Signals936.12 Sense Signals936.13 Ground and Non-Critical to Function (NCTF) Signals936.14 Processor Internal Pull-Up / Pull-Down Terminations937.0 Electrical Specifications947.1 Integrated Voltage Regulator947.2 Power and Ground Lands947.3 VCC Voltage Identification (VID)947.4 Reserved or Unused Signals997.5 Signal Groups997.6 Test Access Port (TAP) Connection1017.7 DC Specifications1017.8 Voltage and Current Specifications1027.8.1 Platform Environment Control Interface (PECI) DC Characteristics1077.8.2 Input Device Hysteresis1088.0 Package Mechanical Specifications1098.1 Processor Component Keep-Out Zone1098.2 Package Loading Specifications1098.3 Package Handling Guidelines1108.4 Package Insertion Specifications1108.5 Processor Mass Specification1108.6 Processor Materials1108.7 Processor Markings1118.8 Processor Land Coordinates1118.9 Processor Storage Specifications1139.0 Processor Ball and Signal Information115Tamanho: 3 MBPáginas: 125Language: EnglishAbrir o manual