ユーザーズマニュアル目次Introduction 1171.1 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture High-Level Overview171.1.1 ARM* Architecture Compliance171.1.2 Features18Figure 11. Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Features181.1.2.1 Multiply/Accumulate (MAC)181.1.2.2 Memory Management191.1.2.3 Instruction Cache191.1.2.4 Branch Target Buffer191.1.2.5 Data Cache191.1.2.6 Power Management201.1.2.7 Interrupt Controller201.1.2.8 Bus Controller201.1.2.9 Performance Monitoring201.1.2.10 Debug201.1.2.11 JTAG201.2 Terminology and Conventions211.2.1 Number Representation211.2.2 Terminology and Acronyms211.3 Other Relevant Documents22Programming Model 2232.1 ARM* Architecture Compliance232.2 ARM* Architecture Implementation Options232.2.1 Big Endian versus Little Endian232.2.2 26-Bit Code232.2.3 Thumb*232.2.4 ARM* DSP-Enhanced Instruction Set242.2.5 Base Register Update242.3 Extensions to ARM* Architecture252.3.1 DSP Coprocessor 0 (CP0)252.3.1.1 Multiply With Internal Accumulate Format26Table 21. Multiply with Internal Accumulate Format26Table 22. MIA{<cond>} acc0, Rm, Rs26Table 23. MIAPH{<cond>} acc0, Rm, Rs27Table 24. MIAxy{<cond>} acc0, Rm, Rs282.3.1.2 Internal Accumulator Access Format29Table 25. Internal Accumulator Access Format29Table 26. MAR{<cond>} acc0, RdLo, RdHi30Table 27. MRA{<cond>} RdLo, RdHi, acc0302.3.2 New Page Attributes31Table 28. First-level Descriptors32Table 29. Second-level Descriptors for Coarse Page Table32Table 210. Second-level Descriptors for Fine Page Table322.3.3 Additions to CP15 Functionality33Example 21. CPWAIT: Canonical method to wait for CP15 update332.3.4 Event Architecture342.3.4.1 Exception Summary34Table 211. Exception Summary342.3.4.2 Event Priority34Table 212. Event Priority342.3.4.3 Prefetch Aborts35Table 213. Intel® 80200 Processor Encoding of Fault Status for Prefetch Aborts352.3.4.4 Data Aborts36Table 214. Intel® 80200 Processor Encoding of Fault Status for Data Aborts36Example 22. Shielding Code from Potential Imprecise Aborts372.3.4.5 Events from Preload Instructions38Example 23. Speculatively issuing PLD382.3.4.6 Debug Events38Memory Management 3393.1 Overview393.2 Architecture Model403.2.1 Version 4 vs. Version 5403.2.2 Memory Attributes403.2.2.1 Page (P) Attribute Bit403.2.2.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits403.2.2.3 Instruction Cache403.2.2.4 Data Cache and Write Buffer41Table 31. Data Cache and Buffer Behavior when X = 041Table 32. Data Cache and Buffer Behavior when X = 1413.2.2.5 Details on Data Cache and Write Buffer Behavior423.2.2.6 Memory Operation Ordering42Table 33. Memory Operations that Impose a Fence423.2.3 Exceptions423.3 Interaction of the MMU, Instruction Cache, and Data Cache43Table 34. Valid MMU & Data/mini-data Cache Combinations433.4 Control443.4.1 Invalidate (Flush) Operation443.4.2 Enabling/Disabling44Example 31. Enabling the MMU443.4.3 Locking Entries45Example 32. Locking Entries into the Instruction TLB45Example 33. Locking Entries into the Data TLB463.4.4 Round-Robin Replacement Algorithm47Figure 31. Example of Locked Entries in TLB47Instruction Cache 4494.1 Overview49Figure 41. Instruction Cache Organization494.2 Operation504.2.1 Operation When Instruction Cache is Enabled504.2.2 Operation When The Instruction Cache Is Disabled504.2.3 Fetch Policy514.2.4 Round-Robin Replacement Algorithm514.2.5 Parity Protection52Example 41. Recovering from an Instruction Cache Parity Error524.2.6 Instruction Fetch Latency534.2.7 Instruction Cache Coherency534.3 Instruction Cache Control544.3.1 Instruction Cache State at RESET544.3.2 Enabling/Disabling54Example 42. Enabling the Instruction Cache544.3.3 Invalidating the Instruction Cache55Example 43. Invalidating the Instruction Cache554.3.4 Locking Instructions in the Instruction Cache56Figure 42. Locked Line Effect on Round Robin Replacement56Example 44. Locking Code into the Cache574.3.5 Unlocking Instructions in the Instruction Cache57Branch Target Buffer 5595.1 Branch Target Buffer (BTB) Operation59Figure 51. BTB Entry59Figure 52. Branch History605.1.1 Reset605.1.2 Update Policy605.2 BTB Control615.2.1 Disabling/Enabling615.2.2 Invalidation61Data Cache 6636.1 Overviews636.1.1 Data Cache Overview63Figure 61. Data Cache Organization646.1.2 Mini-Data Cache Overview65Figure 62. Mini-Data Cache Organization656.1.3 Write Buffer and Fill Buffer Overview666.2 Data Cache and Mini-Data Cache Operation676.2.1 Operation When Caching is Enabled676.2.2 Operation When Data Caching is Disabled676.2.3 Cache Policies676.2.3.1 Cacheability676.2.3.2 Read Miss Policy686.2.3.3 Write Miss Policy696.2.3.4 Write-Back Versus Write-Through696.2.4 Round-Robin Replacement Algorithm706.2.5 Parity Protection706.2.6 Atomic Accesses706.3 Data Cache and Mini-Data Cache Control716.3.1 Data Memory State After Reset716.3.2 Enabling/Disabling71Example 61. Enabling the Data Cache716.3.3 Invalidate & Clean Operations716.3.3.1 Global Clean and Invalidate Operation72Example 62. Global Clean Operation726.4 Re-configuring the Data Cache as Data RAM74Example 63. Locking Data into the Data Cache75Example 64. Creating Data RAM76Figure 63. Locked Line Effect on Round Robin Replacement776.5 Write Buffer/Fill Buffer Operation and Control78Configuration 7797.1 Overview79Table 71. MRC/MCR Format80Table 72. LDC/STC Format817.2 CP15 Registers82Table 73. CP15 Registers827.2.1 Register 0: ID and Cache Type Registers83Table 74. ID Register83Table 75. Cache Type Register (Sheet 1 of 2)837.2.2 Register 1: Control and Auxiliary Control Registers85Table 76. ARM* Control Register85Table 77. Auxiliary Control Register867.2.3 Register 2: Translation Table Base Register87Table 78. Translation Table Base Register877.2.4 Register 3: Domain Access Control Register87Table 79. Domain Access Control Register877.2.5 Register 4: Reserved877.2.6 Register 5: Fault Status Register88Table 710. Fault Status Register887.2.7 Register 6: Fault Address Register88Table 711. Fault Address Register887.2.8 Register 7: Cache Functions89Table 712. Cache Functions897.2.9 Register 8: TLB Operations91Table 713. TLB Functions917.2.10 Register 9: Cache Lock Down92Table 714. Cache Lockdown Functions92Table 715. Data Cache Lock Register927.2.11 Register 10: TLB Lock Down93Table 716. TLB Lockdown Functions937.2.12 Register 11-12: Reserved937.2.13 Register 13: Process ID94Table 717. Accessing Process ID94Table 718. Process ID Register947.2.13.1 The PID Register Affect On Addresses947.2.14 Register 14: Breakpoint Registers95Table 719. Accessing the Debug Registers957.2.15 Register 15: Coprocessor Access Register96Example 71. Disallowing access to CP096Table 720. Coprocessor Access Register977.3 CP14 Registers98Table 721. CP14 Registers987.3.1 Registers 0-3: Performance Monitoring98Table 722. Accessing the Performance Monitoring Registers987.3.2 Register 4-5: Reserved987.3.3 Registers 6-7: Clock and Power Management99Table 723. PWRMODE Register99Table 724. Clock and Power Management99Table 725. CCLKCFG Register997.3.4 Registers 8-15: Software Debug100Table 726. Accessing the Debug Registers100System Management 81018.1 Clocking101Table 81. Reset CCLK Configuration101Table 82. Software CCLK Configuration102Example 81. CCLK Modification Procedure1028.2 Processor Reset1038.2.1 Reset Sequence103Figure 81. Reset Sequence1038.2.2 Reset Effect on Outputs104Figure 82. Pin State at Reset1048.3 Power Management105Table 83. Low Power Modes1058.3.1 Invocation1058.3.2 Signals Associated with Power Management105Table 84. PWRSTATUS[1:0] Encoding105Interrupts 91079.1 Introduction1079.2 External Interrupts1079.3 Programmer Model108Figure 91. Interrupt Controller Block Diagram1089.3.1 INTCTL109Table 91. Interrupt Control Register (CP13 register 0)1099.3.2 INTSRC110Table 92. Interrupt Source Register (CP13, register 4)110Example 91. Waiting for FIQ# Deassertion1109.3.3 INTSTR111Table 93. Interrupt Steer Register (CP13, register 8)111External Bus 1011310.1 General Description113Figure 101. Typical System113Figure 102. Alternate Configuration11410.2 Signal Description115Table 101. Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Bus Signals11510.2.1 Request Bus11610.2.1.1 Intel® 80200 Processor Use of the Request Bus116Table 102. Requests on a 64-bit Bus116Table 103. Requests on a 32-bit Bus11710.2.2 Data Bus11810.2.3 Critical Word First119Table 104. Return Order for 8-Word Burst, 64-bit Data Bus119Table 105. Return Order for 8-Word Burst, 32-bit Data Bus11910.2.4 Configuration Pins12010.2.5 Multimaster Support12110.2.6 Abort12310.2.7 ECC12410.2.8 Big Endian System Configuration125Figure 103. Big Endian Lane Swapping on a 64-bit Bus12510.3 Examples12610.3.1 Simple Read Word126Figure 104. Basic Read Timing12610.3.2 Read Burst, No Critical Word First127Figure 105. Read Burst, No CWF12710.3.3 Read Burst, Critical Word First Data Return128Figure 106. Read Burst, CWF12810.3.4 Word Write129Figure 107. Basic Word Write12910.3.5 Two Word Coalesced Write130Figure 108. Two Word Coalesced Write13010.3.5.1 Write Burst131Figure 109. Four Word Eviction Write13110.3.6 Write Burst, Coalesced132Figure 1010. Four Word Coalesced Write Burst13210.3.7 Pipelined Accesses133Figure 1011. Pipeline Example13310.3.8 Locked Access134Figure 1012. Locked Access13410.3.9 Aborted Access135Figure 1013. Aborted Access13510.3.10 Hold136Figure 1014. Hold Assertion136Bus Controller 1113711.1 Introduction13711.2 ECC13711.3 Error Handling13811.3.1 Bus Aborts13811.3.2 ECC Errors139Table 111. BCU Response to ECC Errors13911.4 Programmer Model14111.4.1 BCU Control Registers141Table 112. BCUCTL (Register 0) (Sheet 1 of 2)141Example 111. Loop to Wait on BCU142Example 112. Enabling ECC142Example 113. Handling BCU Errors143Table 113. BCUMOD (Register 1)14311.4.2 ECC Error Registers145Table 114. ELOG0, ELOG1(Registers 4, 5)145Table 115. ECAR0, ECAR1(Registers 6, 7)145Table 116. ECTST (Register 8)146Performance Monitoring 1214712.1 Overview14712.2 Clock Counter (CCNT; CP14 - Register 1)148Table 121. Clock Count Register (CCNT)14812.3 Performance Count Registers (PMN0 - PMN1; CP14 - Register 2 and 3, Respectively)149Table 122. Performance Monitor Count Register (PMN0 and PMN1)14912.3.1 Extending Count Duration Beyond 32 Bits14912.4 Performance Monitor Control Register (PMNC)150Table 123. Performance Monitor Control Register (CP14, register 0) (Sheet 1 of 2)15012.4.1 Managing PMNC15112.5 Performance Monitoring Events152Table 124. Performance Monitoring Events152Table 125. Some Common Uses of the PMU15312.5.1 Instruction Cache Efficiency Mode15312.5.2 Data Cache Efficiency Mode15412.5.3 Instruction Fetch Latency Mode15412.5.4 Data/Bus Request Buffer Full Mode15512.5.5 Stall/Writeback Statistics15512.5.6 Instruction TLB Efficiency Mode15612.5.7 Data TLB Efficiency Mode15612.6 Multiple Performance Monitoring Run Statistics15712.7 Examples158Example 121. Configuring the Performance Monitor158Example 122. Interrupt Handling158Example 123. Computing the Results158Software Debug 1315913.1 Definitions15913.2 Debug Registers15913.3 Introduction16013.3.1 Halt Mode16013.3.2 Monitor Mode16013.4 Debug Control and Status Register (DCSR)161Table 131. Debug Control and Status Register (DCSR) (Sheet 1 of 2)16113.4.1 Global Enable Bit (GE)16213.4.2 Halt Mode Bit (H)16213.4.3 Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR)16313.4.4 Sticky Abort Bit (SA)16313.4.5 Method of Entry Bits (MOE)16313.4.6 Trace Buffer Mode Bit (M)16313.4.7 Trace Buffer Enable Bit (E)16313.5 Debug Exceptions164Table 132. Event Priority16413.5.1 Halt Mode16413.5.2 Monitor Mode16613.6 HW Breakpoint Resources16713.6.1 Instruction Breakpoints167Table 133. Instruction Breakpoint Address and Control Register (IBCRx)16713.6.2 Data Breakpoints168Table 134. Data Breakpoint Register (DBRx)168Table 135. Data Breakpoint Controls Register (DBCON)16813.7 Software Breakpoints16913.8 Transmit/Receive Control Register (TXRXCTRL)170Table 136. TX RX Control Register (TXRXCTRL)17013.8.1 RX Register Ready Bit (RR)171Table 137. Normal RX Handshaking171Table 138. High-Speed Download Handshaking States17113.8.2 Overflow Flag (OV)17213.8.3 Download Flag (D)17213.8.4 TX Register Ready Bit (TR)173Table 139. TX Handshaking17313.8.5 Conditional Execution Using TXRXCTRL173Table 1310. TXRXCTRL Mnemonic Extensions17313.9 Transmit Register (TX)174Table 1311. TX Register17413.10 Receive Register (RX)174Table 1312. RX Register17413.11 Debug JTAG Access17513.11.1 SELDCSR JTAG Command17513.11.2 SELDCSR JTAG Register176Figure 131. SELDCSR Hardware176Figure 132. SELDCSR Data Register17713.11.2.1 DBG.HLD_RST17713.11.2.2 DBG.BRK17813.11.2.3 DBG.DCSR17813.11.3 DBGTX JTAG Command17813.11.4 DBGTX JTAG Register179Figure 133. DBGTX Hardware17913.11.5 DBGRX JTAG Command17913.11.6 DBGRX JTAG Register180Figure 134. DBGRX Hardware18013.11.6.1 RX Write Logic181Figure 135. RX Write Logic18113.11.6.2 DBGRX Data Register182Figure 136. DBGRX Data Register18213.11.6.3 DBG.RR18213.11.6.4 DBG.V18313.11.6.5 DBG.RX18313.11.6.6 DBG.D18313.11.6.7 DBG.FLUSH18313.11.7 Debug JTAG Data Register Reset Values183Table 1313. DEBUG Data Register Reset Values18313.12 Trace Buffer18413.12.1 Trace Buffer CP Registers184Table 1314. CP 14 Trace Buffer Register Summary18413.12.1.1 Checkpoint Registers184Table 1315. Checkpoint Register (CHKPTx)18413.12.1.2 Trace Buffer Register (TBREG)185Table 1316. TBREG Format18513.13 Trace Buffer Entries18613.13.1 Message Byte186Figure 137. Message Byte Formats186Table 1317. Message Byte Formats18613.13.1.1 Exception Message Byte18713.13.1.2 Non-exception Message Byte188Example 131. Rollover Messages Examples18813.13.1.3 Address Bytes189Figure 138. Indirect Branch Entry Address Byte Organization18913.13.2 Trace Buffer Usage190Figure 139. High Level View of Trace Buffer19013.14 Downloading Code in the ICache19213.14.1 LDIC JTAG Command19213.14.2 LDIC JTAG Data Register193Figure 1310. LDIC JTAG Data Register Hardware19313.14.3 LDIC Cache Functions194Table 1318. LDIC Cache Functions194Figure 1311. Format of LDIC Cache Functions19513.14.4 Loading IC During Reset19613.14.4.1 Loading IC During Cold Reset for Debug197Figure 1312. Code Download During a Cold Reset For Debug19713.14.4.2 Loading IC During a Warm Reset for Debug199Figure 1313. Code Download During a Warm Reset For Debug19913.14.5 Dynamically Loading IC After Reset201Figure 1314. Downloading Code in IC During Program Execution20113.14.5.1 Dynamic Code Download Synchronization20313.14.6 Mini Instruction Cache Overview20413.15 Halt Mode Software Protocol20513.15.1 Starting a Debug Session20513.15.1.1 Setting up Override Vector Tables20513.15.1.2 Placing the Handler in Memory20613.15.2 Implementing a Debug Handler20713.15.2.1 Debug Handler Entry20713.15.2.2 Debug Handler Restrictions20713.15.2.3 Dynamic Debug Handler20813.15.2.4 High-Speed Download21013.15.3 Ending a Debug Session21113.16 Software Debug Notes/Errata212Performance Considerations 1421314.1 Interrupt Latency213Table 141. Minimum Interrupt Latency21314.2 Branch Prediction214Table 142. Branch Latency Penalty21414.3 Addressing Modes21414.4 Instruction Latencies21514.4.1 Performance Terms215Example 141. Computing Latencies216Table 143. Latency Example21614.4.2 Branch Instruction Timings216Table 144. Branch Instruction Timings (Those predicted by the BTB)216Table 145. Branch Instruction Timings (Those not predicted by the BTB)21714.4.3 Data Processing Instruction Timings217Table 146. Data Processing Instruction Timings21714.4.4 Multiply Instruction Timings218Table 147. Multiply Instruction Timings (Sheet 1 of 2)218Table 148. Multiply Implicit Accumulate Instruction Timings219Table 149. Implicit Accumulator Access Instruction Timings21914.4.5 Saturated Arithmetic Instructions220Table 1410. Saturated Data Processing Instruction Timings22014.4.6 Status Register Access Instructions220Table 1411. Status Register Access Instruction Timings22014.4.7 Load/Store Instructions220Table 1412. Load and Store Instruction Timings220Table 1413. Load and Store Multiple Instruction Timings22014.4.8 Semaphore Instructions221Table 1414. Semaphore Instruction Timings22114.4.9 Coprocessor Instructions221Table 1415. CP15 Register Access Instruction Timings221Table 1416. CP14 Register Access Instruction Timings22114.4.10 Miscellaneous Instruction Timing221Table 1417. SWI Instruction Timings221Table 1418. Count Leading Zeros Instruction Timings22114.4.11 Thumb* Instructions221Compatibility: Intel® 80200 Processor vs. SA-110 A223A.1 Introduction223A.2 Summary223A.3 Architecture Deviations225A.3.1 Read Buffer225A.3.2 26-bit Mode225A.3.3 Cacheable (C) and Bufferable (B) Encoding225Table A1. C and B encoding225A.3.4 Write Buffer Behavior226A.3.5 External Aborts226A.3.6 Performance Differences227A.3.7 System Control Coprocessor227A.3.8 New Instructions and Instruction Formats227A.3.9 Augmented Page Table Descriptors227Optimization Guide B229B.1 Introduction229B.1.1 About This Guide229B.2 Intel® 80200 Processor Pipeline230B.2.1 General Pipeline Characteristics230B.2.1.1. Number of Pipeline Stages230B.2.1.2. Intel® 80200 Processor Pipeline Organization231Figure B1. Intel® 80200 Processor RISC Superpipeline231Table B1. Pipelines and Pipe stages231B.2.1.3. Out Of Order Completion232B.2.1.4. Register Scoreboarding232B.2.1.5. Use of Bypassing232B.2.2 Instruction Flow Through the Pipeline233B.2.2.1. ARM* V5 Instruction Execution233B.2.2.2. Pipeline Stalls233B.2.3 Main Execution Pipeline234B.2.3.1. F1 / F2 (Instruction Fetch) Pipestages234B.2.3.2. ID (Instruction Decode) Pipestage234B.2.3.3. RF (Register File / Shifter) Pipestage235B.2.3.4. X1 (Execute) Pipestage235B.2.3.5. X2 (Execute 2) Pipestage235B.2.3.6. WB (write-back)235B.2.4 Memory Pipeline236B.2.4.1. D1 and D2 Pipestage236B.2.5 Multiply/Multiply Accumulate (MAC) Pipeline236B.2.5.1. Behavioral Description236B.3 Basic Optimizations237B.3.1 Conditional Instructions237B.3.1.1. Optimizing Condition Checks237B.3.1.2. Optimizing Branches238B.3.1.3. Optimizing Complex Expressions240B.3.2 Bit Field Manipulation241B.3.3 Optimizing the Use of Immediate Values242B.3.4 Optimizing Integer Multiply and Divide243B.3.5 Effective Use of Addressing Modes244B.4 Cache and Prefetch Optimizations245B.4.1 Instruction Cache245B.4.1.1. Cache Miss Cost245B.4.1.2. Round Robin Replacement Cache Policy245B.4.1.3. Code Placement to Reduce Cache Misses245B.4.1.4. Locking Code into the Instruction Cache246B.4.2 Data and Mini Cache247B.4.2.1. Non Cacheable Regions247B.4.2.2. Write-through and Write-back Cached Memory Regions247B.4.2.3. Read Allocate and Read-write Allocate Memory Regions248B.4.2.4. Creating On-chip RAM248B.4.2.5. Mini-data Cache249B.4.2.6. Data Alignment250B.4.2.7. Literal Pools251B.4.3 Cache Considerations252B.4.3.1. Cache Conflicts, Pollution and Pressure252B.4.3.2. Memory Page Thrashing252B.4.4 Prefetch Considerations253B.4.4.1. Prefetch Distances in the Intel® 80200 Processor253B.4.4.2. Prefetch Loop Scheduling255B.4.4.3. Prefetch Loop Limitations255B.4.4.4. Compute vs. Data Bus Bound255B.4.4.5. Low Number of Iterations255B.4.4.6. Bandwidth Limitations256B.4.4.7. Cache Memory Considerations257B.4.4.8. Cache Blocking259B.4.4.9. Prefetch Unrolling259B.4.4.10. Pointer Prefetch260B.4.4.11. Loop Interchange261B.4.4.12. Loop Fusion261B.4.4.13. Prefetch to Reduce Register Pressure262B.5 Instruction Scheduling263B.5.1 Scheduling Loads263B.5.1.1. Scheduling Load and Store Double (LDRD/STRD)265B.5.1.2. Scheduling Load and Store Multiple (LDM/STM)266B.5.2 Scheduling Data Processing Instructions267B.5.3 Scheduling Multiply Instructions268B.5.4 Scheduling SWP and SWPB Instructions269B.5.5 Scheduling the MRA and MAR Instructions (MRRC/MCRR)270B.5.6 Scheduling the MIA and MIAPH Instructions271B.5.7 Scheduling MRS and MSR Instructions272B.5.8 Scheduling CP15 Coprocessor Instructions272B.6 Optimizing C Libraries273B.7 Optimizations for Size273B.7.1 Space/Performance Trade Off273B.7.1.1. Multiple Word Load and Store273B.7.1.2. Use of Conditional Instructions273B.7.1.3. Use of PLD Instructions273Test Features C275C.1 Introduction275C.2 JTAG - IEEE1149.1275C.2.1 Boundary Scan Architecture276Figure C1. Test Access Port Block Diagram276C.2.2 TAP Pins277Table C1. TAP Controller Pin Definitions 277C.2.3 Instruction Register (IR)278C.2.3.1. Boundary-Scan Instruction Set278Table C2. JTAG Instruction Set278Table C3. IEEE Instructions279C.2.4 TAP Test Data Registers280C.2.4.1. Device Identification Register280Table C4. JTAG ID Register Value280C.2.4.2. Bypass Register280C.2.4.3. Boundary-Scan Register280C.2.5 TAP Controller281Figure C2. TAP Controller State Diagram281C.2.5.1. Test Logic Reset State282C.2.5.2. Run-Test/Idle State282C.2.5.3. Select-DR-Scan State282C.2.5.4. Capture-DR State282C.2.5.5. Shift-DR State283C.2.5.6. Exit1-DR State283C.2.5.7. Pause-DR State283C.2.5.8. Exit2-DR State283C.2.5.9. Update-DR State284C.2.5.10. Select-IR Scan State284C.2.5.11. Capture-IR State284C.2.5.12. Shift-IR State284C.2.5.13. Exit1-IR State285C.2.5.14. Pause-IR State285C.2.5.15. Exit2-IR State285C.2.5.16. Update-IR State285C.2.5.17. Boundary-Scan Example286Figure C3. JTAG Example287Figure C4. Timing Diagram Illustrating the Loading of Instruction Register288Figure C5. Timing Diagram Illustrating the Loading of Data Register289サイズ: 2.83MBページ数: 289Language: Englishマニュアルを開く