データシート目次Low-Power Features:3LCD Driver and Keypad Features:3Peripheral Highlights:3Special Microcontroller Features:4Pin Diagrams – PIC18F6XK905Pin Diagrams – PIC18F8XK906Table of Contents71.0 Device Overview91.1 Core Features91.1.1 nanoWatt Technology91.1.2 Oscillator Options and Features91.1.3 Memory Options91.1.4 Extended Instruction Set91.1.5 Easy Migration91.2 LCD Driver101.3 Other Special Features101.4 Details on Individual Family Members10TABLE 1-1: Device Features for the PIC18F6XK90 (64-pin Devices)11TABLE 1-2: Device Features for the PIC18F8XK90 (80-pin Devices)11FIGURE 1-1: PIC18F6XK90 (64-pin) Block Diagram12FIGURE 1-2: PIC18F8XK90 (80-pin) Block Diagram13TABLE 1-3: PIC18F6XK90 Pinout I/O Descriptions14TABLE 1-4: PIC18F8XK90 Pinout I/O Descriptions222.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers352.1 Basic Connection Requirements35FIGURE 2-1: Recommended Minimum connections352.2 Power Supply Pins362.2.1 Decoupling Capacitors362.2.2 Tank Capacitors362.3 Master Clear (MCLR) Pin36FIGURE 2-2: Example of MCLR Pin Connections362.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)37FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap37TABLE 2-1: Suitable Capacitor Equivalents372.4.1 Considerations for Ceramic Capacitors38FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics382.5 ICSP Pins382.6 External Oscillator Pins392.7 Unused I/Os39FIGURE 2-5: Suggested Placement of the Oscillator Circuit393.0 Oscillator Configurations413.1 Oscillator Types41TABLE 3-1: HS, EC, XT, LP and RC Modes: Ranges and Settings42FIGURE 3-1: PIC18F87K90 Family Clock Diagram423.2 Control Registers43Register 3-1: OSCCON: Oscillator Control Register43Register 3-2: OSCCON2: Oscillator Control Register 244Register 3-3: OSCTUNE: Oscillator Tuning Register453.3 Clock Sources and Oscillator Switching453.3.1 OSC1/OSC2 Oscillator463.3.2 Clock Source Selection463.3.3 Oscillator Transitions463.4 External Oscillator Modes463.4.1 Crystal Oscillator/Ceramic Resonators (HS Modes)46TABLE 3-2: Capacitor Selection for Ceramic Resonators47TABLE 3-3: Capacitor Selection for Crystal Oscillator47FIGURE 3-2: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)473.5 RC Oscillator47FIGURE 3-3: RC Oscillator Mode48FIGURE 3-4: RCIO Oscillator Mode483.5.1 External Clock Input (EC Modes)48FIGURE 3-5: External Clock Input Operation (EC Configuration)48FIGURE 3-6: External Clock Input Operation (HS OSC Configuration)483.5.2 PLL Frequency Multiplier48FIGURE 3-7: PLL Block Diagram493.6 Internal Oscillator Block493.6.1 INTIO Modes49FIGURE 3-8: INTIO1 Oscillator Mode49FIGURE 3-9: INTIO2 Oscillator Mode493.6.2 INTPLL Modes503.6.3 Internal Oscillator Output Frequency and Tuning503.6.4 INTOSC Frequency Drift503.7 Reference Clock Output51Register 3-4: REFOCON: Reference Oscillator Control Register513.8 Effects of Power-Managed Modes on the Various Clock Sources523.9 Power-up Delays52TABLE 3-4: OSC1 and OSC2 Pin States in Sleep Mode524.0 Power-Managed Modes534.1 Selecting Power-Managed Modes534.1.1 Clock Sources534.1.2 Entering Power-Managed Modes53TABLE 4-1: Power-Managed Modes534.1.3 Clock Transitions and Status Indicators54TABLE 4-2: System Clock Indicator544.1.4 Multiple Sleep Commands544.2 Run Modes544.2.1 PRI_RUN Mode544.2.2 SEC_RUN Mode54FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode55FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)554.2.3 RC_RUN Mode55TABLE 4-3: Internal Oscillator Frequency Stability Bits56FIGURE 4-3: Transition Timing to RC_RUN Mode57FIGURE 4-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode574.3 Sleep Mode584.4 Idle Modes58FIGURE 4-5: Transition Timing for Entry to Sleep Mode58FIGURE 4-6: Transition Timing for Wake From Sleep (HSPLL)584.4.1 PRI_IDLE Mode594.4.2 SEC_IDLE Mode59FIGURE 4-7: Transition Timing for Entry to Idle Mode59FIGURE 4-8: Transition Timing for Wake From Idle to Run Mode594.4.3 RC_IDLE Mode604.5 Selective Peripheral Module Control60Register 4-1: PMD3: Peripheral Module Disable Register 361Register 4-2: PMD2: Peripheral Module Disable Register 262Register 4-3: PMD1: Peripheral Module Disable Register 163Register 4-4: PMD0: Peripheral Module Disable Register 0644.6 Exiting Idle and Sleep Modes654.6.1 Exit By Interrupt654.6.2 Exit By WDT Time-out654.6.3 Exit By Reset654.6.4 Exit Without an Oscillator Start-up Delay654.7 Ultra Low-Power Wake-up66EXAMPLE 4-1: Ultra Low-Power Wake-up Initialization66FIGURE 4-9: Ultra Low-Power Wake-up Initialization66TABLE 4-4: Exit Delay on Wake-up By Reset From Sleep Mode or Any Idle Mode (By Clock Sources)675.0 Reset695.1 RCON Register69FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit69Register 5-1: RCON: Reset Control Register705.2 Master Clear (MCLR)715.3 Power-on Reset (POR)715.4 Brown-out Reset (BOR)71FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)715.4.1 Detecting BOR715.5 Configuration Mismatch (CM)725.6 Power-up Timer (PWRT)725.6.1 Time-out Sequence72FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)72FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 173FIGURE 5-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 273FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)735.7 Reset State of Registers74TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register74TABLE 5-2: Initialization Conditions for All Registers756.0 Memory Organization85FIGURE 6-1: Memory Maps for PIC18F87K90 Family Devices856.1 Program Memory Organization866.1.1 Hard Memory Vectors86FIGURE 6-2: Hard Vector for PIC18F87K90 Family Devices866.1.2 Program Counter876.1.3 Return Address Stack87FIGURE 6-3: Return Address Stack and Associated Registers87Register 6-1: STKPTR: Stack Pointer Register886.1.4 Fast Register Stack89EXAMPLE 6-1: Fast Register Stack Code Example896.1.5 Look-up Tables in Program Memory89EXAMPLE 6-2: Computed GOTO Using an Offset Value896.2 PIC18 Instruction Cycle906.2.1 Clocking Scheme906.2.2 Instruction Flow/Pipelining90FIGURE 6-4: Clock/ Instruction Cycle90EXAMPLE 6-3: Instruction Pipeline Flow906.2.3 Instructions in Program Memory91FIGURE 6-5: Instructions in Program Memory916.2.4 Two-Word Instructions91EXAMPLE 6-4: Two-Word Instructions916.3 Data Memory Organization926.3.1 Bank Select Register92FIGURE 6-6: Data Memory Map for PIC18FX5K90 and PIC18FX7K90 Devices93FIGURE 6-7: Use of the Bank Select Register (Direct Addressing)946.3.2 Access Bank946.3.3 General Purpose Register File946.3.4 Special Function Registers95TABLE 6-1: PIC18F87K90 Family Special Function Register Map(5)95TABLE 6-2: PIC18F87K90 Family Register File Summary976.3.5 STATUS Register103Register 6-2: Status Register1036.4 Data Addressing Modes1046.4.1 Inherent and Literal Addressing1046.4.2 Direct Addressing1046.4.3 Indirect Addressing104EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing104FIGURE 6-8: Indirect Addressing1056.5 Program Memory and the Extended Instruction Set1066.6 Data Memory and the Extended Instruction Set1076.6.1 Indexed Addressing with Literal Offset1076.6.2 Instructions Affected By Indexed Literal Offset Mode107FIGURE 6-9: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)1086.6.3 Mapping the Access Bank in Indexed Literal Offset Mode1096.6.4 BSR in Indexed Literal Offset Mode109FIGURE 6-10: Remapping the Access Bank with Indexed Literal Offset Addressing1097.0 Flash Program Memory1117.1 Table Reads and Table Writes111FIGURE 7-1: Table Read Operation111FIGURE 7-2: Table Write Operation1127.2 Control Registers1127.2.1 EECON1 and EECON2 Registers112Register 7-1: EECON1: EEPROM Control Register 11137.2.2 TABLAT – Table Latch Register1147.2.3 TBLPTR – Table Pointer Register1147.2.4 Table Pointer Boundaries114TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions114FIGURE 7-3: Table Pointer Boundaries Based on Operation1147.3 Reading the Flash Program Memory115FIGURE 7-4: Reads From Flash Program Memory115EXAMPLE 7-1: Reading a Flash Program Memory Word1157.4 Erasing Flash Program Memory1167.4.1 Flash Program Memory Erase Sequence116EXAMPLE 7-2: Erasing a Flash Program Memory Row1167.5 Writing to Flash Program Memory117FIGURE 7-5: Table Writes to Flash Program Memory1177.5.1 Flash Program Memory Write Sequence117EXAMPLE 7-3: Writing to Flash Program Memory118EXAMPLE 7-3: Writing to Flash Program Memory (Continued)1197.5.2 Write Verify1197.5.3 Unexpected Termination of Write Operation1197.5.4 Protection Against Spurious Writes1197.6 Flash Program Operation During Code Protection119TABLE 7-2: Registers Associated with Program Flash Memory1198.0 Data EEPROM Memory1218.1 EEADR and EEADRH Registers1218.2 EECON1 and EECON2 Registers121Register 8-1: EECON1: Data EEPROM Control Register 11228.3 Reading the Data EEPROM Memory1238.4 Writing to the Data EEPROM Memory1238.5 Write Verify123EXAMPLE 8-1: Data EEPROM Read123EXAMPLE 8-2: Data EEPROM Write1238.6 Operation During Code-Protect1248.7 Protection Against Spurious Write1248.8 Using the Data EEPROM124EXAMPLE 8-3: Data EEPROM Refresh Routine124TABLE 8-1: Registers Associated with Data EEPROM Memory1259.0 8 X 8 Hardware Multiplier1279.1 Introduction1279.2 Operation127EXAMPLE 9-1: 8 x 8 Unsigned Multiply Routine127EXAMPLE 9-2: 8 x 8 Signed Multiply Routine127TABLE 9-1: Performance Comparison for Various Multiply Operations127EQUATION 9-1: 16 x 16 Unsigned Multiplication Algorithm128EXAMPLE 9-3: 16 x 16 Unsigned Multiply Routine128EQUATION 9-2: 16 x 16 Signed Multiplication Algorithm128EXAMPLE 9-4: 16 x 16 Signed Multiply Routine12810.0 Interrupts129FIGURE 10-1: PIC18F87K90 Family Interrupt Logic13010.1 INTCON Registers131Register 10-1: INTCON: Interrupt Control Register131Register 10-2: INTCON2: Interrupt Control Register 2132Register 10-3: INTCON3: Interrupt Control Register 313310.2 PIR Registers134Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1134Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2135Register 10-6: PIR3: Peripheral Interrupt Request (Flag) Register 3136Register 10-7: PIR4: Peripheral Interrupt Flag Register 4137Register 10-8: PIR5: Peripheral Interrupt Flag Register 5138Register 10-9: PIR6: Peripheral Interrupt Flag Register 613910.3 PIE Registers140Register 10-10: PIE1: Peripheral Interrupt Enable Register 1140Register 10-11: PIE2: Peripheral Interrupt Enable Register 2141Register 10-12: PIE3: Peripheral Interrupt Enable Register 3142Register 10-13: PIE4: Peripheral Interrupt Enable Register 4142Register 10-14: PIE5: Peripheral Interrupt Enable Register 5143Register 10-15: PIE6: Peripheral Interrupt Enable Register 614410.4 IPR Registers145Register 10-16: IPR1: Peripheral Interrupt Priority Register 1145Register 10-17: IPR2: Peripheral Interrupt Priority Register 2146Register 10-18: IPR3: Peripheral Interrupt Priority Register 3147Register 10-19: IPR4: Peripheral Interrupt Priority Register 4147Register 10-20: IPR5: Peripheral Interrupt Priority Register 5148Register 10-21: IPR6: Peripheral Interrupt Priority Register 614910.5 RCON Register150Register 10-22: RCON: Reset Control Register15010.6 INTx Pin Interrupts15110.7 TMR0 Interrupt15110.8 PORTB Interrupt-on-Change15110.9 Context Saving During Interrupts151EXAMPLE 10-1: Saving STATUS, WREG and BSR Registers in RAM151TABLE 10-1: Summary of Registers Associated with Interrupts15211.0 I/O Ports153FIGURE 11-1: Generic I/O Port Operation15311.1 I/O Port Pin Capabilities15311.1.1 Pin Output Drive15311.1.2 Pull-up Configuration15311.1.3 Open-Drain Outputs154FIGURE 11-2: Using the Open-Drain Output (USART Shown as Example)154Register 11-1: ODCON1: Peripheral Open-Drain Control Register 1154Register 11-2: ODCON2: Peripheral Open-Drain Control Register 2155Register 11-3: ODCON3: Peripheral Open-Drain Control Register 315611.1.4 Analog and Digital Ports15611.2 PORTA, TRISA and LATA Registers157EXAMPLE 11-1: Initializing PORTA157TABLE 11-1: PORTA Functions158TABLE 11-2: Summary of Registers Associated with PORTA15911.3 PORTB, TRISB and LATB Registers160EXAMPLE 11-2: Initializing PORTB160TABLE 11-3: PORTB Functions161TABLE 11-4: Summary of Registers Associated with PORTB16211.4 PORTC, TRISC and LATC Registers163EXAMPLE 11-3: Initializing PORTC163TABLE 11-5: PORTC Functions164TABLE 11-6: Summary of Registers Associated with PORTC16511.5 PORTD, TRISD and LATD Registers166EXAMPLE 11-4: Initializing PORTD166TABLE 11-7: PORTD Functions167TABLE 11-8: Summary of Registers Associated with PORTD16811.6 PORTE, TRISE and LATE Registers169TABLE 11-9: PORTE Pins Available in Different LCD Drive Configurations(1)169EXAMPLE 11-5: Initializing PORTE169TABLE 11-10: PORTE Functions170TABLE 11-11: Summary of Registers Associated with PORTE17111.7 PORTF, LATF and TRISF Registers172EXAMPLE 11-6: Initializing PORTF172TABLE 11-12: PORTF Functions173TABLE 11-13: Summary of Registers Associated with PORTF17411.8 PORTG, TRISG and LATG Registers175EXAMPLE 11-7: Initializing PORTG175TABLE 11-14: PORTG Functions175TABLE 11-15: Summary of Registers Associated with PORTG17611.9 PORTH, LATH and TRISH Registers177EXAMPLE 11-8: Initializing PORTH177TABLE 11-16: PORTH Functions178TABLE 11-17: Summary of Registers Associated with PORTH17911.10 PORTJ, TRISJ and LATJ Registers180EXAMPLE 11-9: Initializing PORTJ180TABLE 11-18: PORTJ Functions181TABLE 11-19: Summary of Registers Associated with PORTJ18112.0 Timer0 Module183Register 12-1: T0CON: Timer0 Control Register18312.1 Timer0 Operation18412.2 Timer0 Reads and Writes in 16-Bit Mode184FIGURE 12-1: Timer0 Block Diagram (8-bit Mode)184FIGURE 12-2: Timer0 Block Diagram (16-bit Mode)18412.3 Prescaler18512.3.1 Switching Prescaler Assignment18512.4 Timer0 Interrupt185TABLE 12-1: Registers Associated with Timer018513.0 Timer1 Module187Register 13-1: T1CON: Timer1 Control Register18713.1 Timer1 Gate Control Register188Register 13-2: T1GCON: Timer1 Gate Control Register(1)18813.2 Timer1 Operation18913.3 Clock Source Selection18913.3.1 INTERNAL CLOCK SOURCE18913.3.2 EXTERNAL CLOCK SOURCE189TABLE 13-1: Timer1 Clock Source Selection189FIGURE 13-1: Timer1 Block Diagram19013.4 Timer1 16-Bit Read/Write Mode19113.5 SOSC Oscillator191FIGURE 13-2: External Components for the SOSC Oscillator191TABLE 13-2: Capacitor Selection for the Timer Oscillator(2,3,4,5)19113.5.1 Using SOSC as a Clock Source19213.5.2 SOSC Oscillator Layout Considerations192FIGURE 13-3: Oscillator Circuit with Grounded Guard Ring19213.6 Timer1 Interrupt19213.7 Resetting Timer1 Using the ECCP Special Event Trigger19313.8 Timer1 Gate19313.8.1 TIMER1 GATE COUNT ENABLE193TABLE 13-3: TIMER1 GATE ENABLE SELECTIONS193FIGURE 13-4: Timer1 Gate Count Enable Mode19313.8.2 TIMER1 GATE SOURCE SELECTION194TABLE 13-4: TIMER1 GATE SOURCES19413.8.3 TIMER1 GATE TOGGLE MODE195FIGURE 13-5: Timer1 Gate Toggle Mode19513.8.4 TIMER1 GATE SINGLE PULSE MODE19613.8.5 TIMER1 GATE VALUE STATUS196FIGURE 13-6: Timer1 Gate Single Pulse Mode196FIGURE 13-7: Timer1 Gate Single Pulse and Toggle Combined Mode197TABLE 13-5: Registers Associated with Timer1 as a Timer/Counter19714.0 Timer2 Module19914.1 Timer2 Operation199Register 14-1: T2CON: Timer2 Control Register19914.2 Timer2 Interrupt20014.3 Timer2 Output200FIGURE 14-1: Timer2 Block Diagram200TABLE 14-1: Registers Associated with Timer2 as a Timer/Counter20015.0 Timer3/5/7 Modules201Register 15-1: TxCON: Timer3/5/7 Control Register20215.1 Timer3/5/7 Gate Control Register203Register 15-2: TxGCON: Timer3/5/7 Gate Control Register(1)203Register 15-3: OSCCON2: Oscillator Control Register 220415.2 Timer3/5/7 Operation205FIGURE 15-1: Timer3/5/7 Block Diagram20515.3 Timer3/5/7 16-Bit Read/Write Mode20615.4 Using the SOSC Oscillator as the Timer3/5/7 Clock Source20615.5 Timer3/5/7 Gates20615.5.1 TIMER3/5/7 GATE COUNT ENABLE206TABLE 15-1: TIMER3/5/7 GATE ENABLE SELECTIONS206FIGURE 15-2: Timer3/5/7 Gate Count Enable Mode20615.5.2 TIMER3/5/7 GATE SOURCE SELECTION207TABLE 15-2: TIMER3/5/7 GATE SOURCES20715.5.3 TIMER3/5/7 GATE TOGGLE MODE207FIGURE 15-3: Timer3/5/7 Gate Toggle Mode20715.5.4 TIMER3/5/7 GATE SINGLE PULSE MODE208FIGURE 15-4: Timer3/5/7 Gate Single Pulse Mode208FIGURE 15-5: Timer3/5/7 Gate Single Pulse and Toggle Combined Mode20915.5.5 TIMER3/5/7 GATE VALUE STATUS20915.5.6 TIMER3/5/7 GATE EVENT INTERRUPT20915.6 Timer3/5/7 Interrupt210TABLE 15-3: Timer3/5/7 Interrupt Flag Bits210TABLE 15-4: Timer3/5/7 Interrupt Enable Bits21015.7 Resetting Timer3/5/7 Using the ECCP Special Event Trigger210TABLE 15-5: Registers Associated with Timer3/5/7 as a Timer/Counter21116.0 Timer4/6/8/10/12 Modules21316.1 Timer4/6/8/10/12 Operation213TABLE 16-1: Timer4/6/8/10/12 Flag Bits213TABLE 16-2: Timer4/6/8/10/12 Interrupt Enable Bits213Register 16-1: TxCON: Timer4/6/8/10/12 Control Register21416.2 Timer4/6/8/10/12 Interrupt21516.3 Output of TMRx215FIGURE 16-1: Timer4/6/8/10/12 Block Diagram215TABLE 16-3: Registers Associated with Timer4/6/8/10/12 as a Timer/Counter21517.0 Real-Time Clock and Calendar (RTCC)217FIGURE 17-1: RTCC Block Diagram21717.1 RTCC Module Registers218RTCC Control Registers218RTCC Value Registers218Alarm Value Registers21817.1.1 RTCC Control Registers219Register 17-1: RTCCFG: RTCC Configuration Register(1)219Register 17-2: RTCCAL: RTCC Calibration Register220Register 17-3: PADCFG1: Pad Configuration Register220Register 17-4: ALRMCFG: Alarm Configuration Register221Register 17-5: ALRMRPT: Alarm Repeat Register22217.1.2 RTCVALH and RTCVALL Register Mappings222Register 17-6: Reserved Register222Register 17-7: Year: Year Value Register(1)223Register 17-8: MontH: Month Value Register(1)223Register 17-9: Day: Day Value Register(1)224Register 17-10: Weekday: Weekday Value Register(1)224Register 17-11: Hour: Hour Value Register(1)225Register 17-12: MINUTE: Minute Value Register225Register 17-13: SECOND: Second Value Register22517.1.3 ALRMVALH and ALRMVALL Register Mappings226Register 17-14: ALRMMNTH: Alarm Month Value Register(1)226Register 17-15: ALRMDAY: Alarm Day Value Register(1)226Register 17-16: ALRMWd: Alarm Weekday Value Register(1)227Register 17-17: ALRMHr: Alarm Hours Value Register(1)227Register 17-18: ALRMMIN: Alarm Minutes Value Register228Register 17-19: ALRMSEC: Alarm Seconds Value Register22817.1.4 RTCEN Bit Write22917.2 Operation22917.2.1 Register Interface229FIGURE 17-2: Timer Digit Format229FIGURE 17-3: Alarm Digit Format22917.2.2 Clock Source230FIGURE 17-4: Clock Source Multiplexing23017.2.3 Digit Carry Rules230TABLE 17-1: Day of Week Schedule230TABLE 17-2: Day-to-Month Rollover Schedule23017.2.4 Leap Year23117.2.5 General Functionality23117.2.6 Safety Window for Register Reads and Writes23117.2.7 Write Lock231EXAMPLE 17-1: Setting the RTCWREN Bit23117.2.8 Register Mapping231TABLE 17-3: RTCVALH and RTCVALL Register Mapping231TABLE 17-4: ALRMVAL Register Mapping23217.2.9 Calibration232EQUATION 17-1: Converting Error Clock Pulses23217.3 Alarm23217.3.1 Configuring the Alarm232FIGURE 17-5: Alarm Mask Settings23317.3.2 Alarm Interrupt233FIGURE 17-6: Timer Pulse Generation23417.4 Sleep Mode23417.5 Reset23417.5.1 Device Reset23417.5.2 Power-on Reset (POR)23417.6 Register Maps235TABLE 17-5: RTCC Control Registers235TABLE 17-6: RTCC Value Registers235TABLE 17-7: Alarm Value Registers23518.0 Capture/Compare/PWM (CCP) Modules237Register 18-1: CCPxCON: CCPx Control Register (CCP4-CCP10 Modules)(1)237Register 18-2: CCPTMRS1: CCPx Timer Select Register 1238Register 18-3: CCPTMRS2: CCPx Timer Select Register 2239Register 18-4: CCPRxL: CCPx Period Low Byte Register240Register 18-5: CCPRxH: CCPx Period High Byte Register24018.1 CCP Module Configuration24118.1.1 CCP Modules and Timer Resources241TABLE 18-1: CCP Mode – Timer Resource241TABLE 18-2: Timer Assignments for CCP Modules 4, 5, 6 and 7241TABLE 18-3: Timer Assignments for CCP Modules 8, 9 and 1024118.1.2 Open-Drain Output Option24218.1.3 Pin Assignment For CCP6, CCP7, CCP8 and CCP9242TABLE 18-4: CCP Pin Assignment24218.2 Capture Mode24218.2.1 CCP Pin Configuration24218.2.2 Timer1/3/5/7 Mode Selection242FIGURE 18-1: Capture Mode Operation Block Diagram24318.2.3 Software Interrupt24318.2.4 CCP Prescaler243EXAMPLE 18-1: Changing Between Capture Prescalers24318.3 Compare Mode24418.3.1 CCP Pin Configuration24418.3.2 Timer1/3/5/7 Mode Selection24418.3.3 Software Interrupt Mode24418.3.4 Special Event Trigger244FIGURE 18-2: Compare Mode Operation Block Diagram245TABLE 18-5: Registers Associated with Capture, Compare, Timer1/3/5/724618.4 PWM Mode247FIGURE 18-3: Simplified PWM Block Diagram247FIGURE 18-4: PWM Output24818.4.1 PWM Period248EQUATION 18-1:24818.4.2 PWM Duty Cycle248EQUATION 18-2:248EQUATION 18-3:248TABLE 18-6: Example PWM Frequencies and Resolutions at 40 MHz24818.4.3 Setup for PWM Operation249TABLE 18-7: Registers Associated with PWM and Timers24919.0 Enhanced Capture/Compare/PWM (ECCP) Module251Register 19-1: CCPxCON: Enhanced Capture/Compare/PWM x Control252Register 19-2: CCPTMRS0: CCP Timer Select 0 Register25319.1 ECCP Outputs and Configuration25419.1.1 ECCP Module and Timer Resources254TABLE 19-1: ECCP Mode – Timer Resource25419.1.2 ECCP Pin Assignment25419.2 Capture Mode255TABLE 19-2: ECCP1/2/3 Interrupt Flag Bits25519.2.1 ECCP Pin Configuration25519.2.2 Timer1/Timer3 Mode Selection25519.2.3 Software Interrupt25519.2.4 ECCP Prescaler255EXAMPLE 19-1: Changing Between Capture Prescalers255FIGURE 19-1: Capture Mode Operation Block Diagram25519.3 Compare Mode25619.3.1 ECCP Pin Configuration25619.3.2 Timer1/Timer3 Mode Selection25619.3.3 Software Interrupt Mode25619.3.4 Special Event Trigger256FIGURE 19-2: Compare Mode Operation Block Diagram25619.4 PWM (Enhanced Mode)257FIGURE 19-3: Example Simplified Block Diagram of the Enhanced PWM Mode257TABLE 19-3: Example Pin Assignments for Various PWM Enhanced Modes258FIGURE 19-4: Example PWM (enhanced Mode) Output Relationships (Active-High State)258FIGURE 19-5: Example Enhanced PWM Output Relationships (Active-Low State)25919.4.1 Half-Bridge Mode260FIGURE 19-6: Example of Half-Bridge PWM Output260FIGURE 19-7: Example of Half-Bridge Applications26019.4.2 Full-Bridge Mode261FIGURE 19-8: Example of Full-Bridge Application261FIGURE 19-9: Example of Full-Bridge PWM Output262FIGURE 19-10: Example of PWM Direction Change263FIGURE 19-11: Example of PWM Direction Change at Near 100% Duty Cycle(1)26419.4.3 Start-up Considerations26419.4.4 Enhanced PWM Auto-shutdown mode264Register 19-3: ECCPxAS: ECCPx Auto-Shutdown Control Register265FIGURE 19-12: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)26619.4.5 Auto-Restart Mode266FIGURE 19-13: PWM Auto-shutdown With Auto-Restart Enabled (PxRSEN = 1)26619.4.6 Programmable Dead-Band Delay Mode267FIGURE 19-14: Example of Half-Bridge PWM Output267FIGURE 19-15: Example of Half-Bridge Applications267Register 19-4: ECCPxDEL: Enhanced PWM Control Register26819.4.7 Pulse Steering Mode268Register 19-5: PSTRxCON: Pulse Steering Control(1)269FIGURE 19-16: Simplified Steering Block Diagram270FIGURE 19-17: Example of Steering Event at End of Instruction (STRSYNC = 0)270FIGURE 19-18: Example of Steering Event at Beginning of Instruction (STRSYNC = 1)27019.4.8 Operation in Power-Managed Modes27119.4.9 Effects of a Reset271TABLE 19-4: Registers Associated with ECCP1/2/3 Module and Timer1/2/3/4/6/8/10/1227220.0 Liquid Crystal Display (LCD) Driver Module273FIGURE 20-1: LCD Driver Module Block Diagram27320.1 LCD Registers274Register 20-1: LCDCON: LCD Control Register274Register 20-2: LCDPS: LCD Phase Register275Register 20-3: LCDREF: LCD Reference Voltage Control Register276Register 20-4: LCDRL: LCD Reference Ladder Control Register277TABLE 20-1: LCDSE Registers and Associated Segments278Register 20-5: LCDSEx: LCD Segmentx Enable Register278TABLE 20-2: LCDDATA Registers and Bits for Segment and COM Combinations279Register 20-6: LCDDATAx: LCD Datax Register27920.2 LCD Clock Source Selection28020.2.1 LCD Prescaler280FIGURE 20-2: LCD Clock Generation28020.3 LCD Bias Types28120.3.1 External resistor biasing281FIGURE 20-3: LCD BIAS External Resistor Ladder Connection diagram28120.3.2 Internal resistor biasing282TABLE 20-3: Internal Resistance Ladder Power Modes282FIGURE 20-4: LCD BIAS Internal Resistor Ladder Connection diagram282FIGURE 20-5: LCD REFERENCE LADDER POWER MODE SWITCHING DIAGRAM283FIGURE 20-6: INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM28420.4 LCD Multiplex Types285TABLE 20-4: PORTE<6:4> Function28520.5 Segment Enables28520.6 Pixel Control28520.7 LCD Frame Frequency286TABLE 20-5: Frame Frequency Formulas286TABLE 20-6: Approximate Frame Frequency (in Hz) Using Fosc at 32 MHz, Timer1 at 32.768 kHz or INTRC Osc28620.8 LCD Waveform Generation286FIGURE 20-7: Type-A/Type-B Waveforms in Static Drive287FIGURE 20-8: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive288FIGURE 20-9: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive289FIGURE 20-10: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive290FIGURE 20-11: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive291FIGURE 20-12: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive292FIGURE 20-13: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive293FIGURE 20-14: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive294FIGURE 20-15: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive295FIGURE 20-16: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive296FIGURE 20-17: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive29720.9 LCD Interrupts298FIGURE 20-18: Example Waveforms and Interrupt Timing in Quarter Duty Cycle Drive29820.10 Operation During Sleep299FIGURE 20-19: Sleep Entry/Exit When SLPEN = 1 or CS<1:0> = 0029920.11 Configuring the LCD Module300TABLE 20-7: Registers Associated with LCD Operation30121.0 Master Synchronous Serial Port (MSSP) Module30321.1 Master SSP (MSSP) Module Overview30321.2 Control Registers30321.3 SPI Mode303FIGURE 21-1: MSSPx Block Diagram (SPI Mode)30321.3.1 Registers304Register 21-1: SSPxSTAT: MSSPx Status Register (SPI Mode)304Register 21-2: SSPxCON1: MSSPx Control Register 1 (SPI Mode)30521.3.2 Operation30621.3.3 OPEN-DRAIN OUTPUT OPTION306EXAMPLE 21-1: Loading the SSP1BUF (SSP1SR) Register30621.3.4 Enabling SPI I/O30721.3.5 Typical Connection307FIGURE 21-2: SPI Master/Slave Connection30721.3.6 Master Mode308FIGURE 21-3: SPI Mode Waveform (Master Mode)30821.3.7 Slave Mode30921.3.8 Slave Select Synchronization309FIGURE 21-4: Slave Synchronization Waveform309FIGURE 21-5: SPI Mode Waveform (Slave Mode with CKE = 0)310FIGURE 21-6: SPI Mode Waveform (Slave Mode with CKE = 1)31021.3.9 Operation in Power-Managed Modes31121.3.10 Effects of a Reset31121.3.11 Bus Mode Compatibility311TABLE 21-1: SPI Bus Modes31121.3.12 SPI Clock Speed and Module Interactions311TABLE 21-2: Registers Associated with SPI Operation31221.4 I2C™ Mode313FIGURE 21-7: MSSPx Block Diagram (I2C™ Mode)31321.4.1 Registers313Register 21-3: SSPxSTAT: MSSPx Status Register (I2C™ Mode)314Register 21-4: SSPxCON1: MSSPx Control Register 1 (I2C™ Mode)315Register 21-5: SSPxCON2: MSSPx Control Register 2 (I2C™ Master Mode)316Register 21-6: SSPxCON2: MSSPx Control Register 2 (I2C™ Slave Mode)317Register 21-7: SSPxMSK: I2C™ Slave Address Mask Register (7-bit Masking Mode)(1)31721.4.2 Operation31821.4.3 Slave Mode318EXAMPLE 21-2: Address Masking Examples in 5-bit Masking Mode319EXAMPLE 21-3: Address Masking Examples in 7-Bit Masking Mode320FIGURE 21-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)322FIGURE 21-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Address)323FIGURE 21-10: I2C™ Slave Mode Timing (Transmission, 7-bit Address)324FIGURE 21-11: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Address)325FIGURE 21-12: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)326FIGURE 21-13: I2C™ Slave Mode Timing (Transmission, 10-bit Address)32721.4.4 Clock Stretching328FIGURE 21-14: Clock Synchronization Timing329FIGURE 21-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)330FIGURE 21-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)33121.4.5 General Call Address Support332FIGURE 21-17: Slave Mode General Call Address Sequence (7 or 10-bit Addressing Mode)33221.4.6 Master Mode333FIGURE 21-18: MSSP Block Diagram (I2C™ Master Mode)33321.4.7 Baud Rate335FIGURE 21-19: Baud Rate Generator Block Diagram335TABLE 21-3: I2C™ Clock Rate w/BRG335FIGURE 21-20: Baud Rate Generator Timing with Clock Arbitration33621.4.8 I2C™ Master Mode Start Condition Timing337FIGURE 21-21: First Start Bit Timing33721.4.9 I2C™ Master Mode Repeated Start Condition Timing338FIGURE 21-22: Repeated Start Condition Waveform33821.4.10 I2C™ Master Mode Transmission33921.4.11 I2C Master Mode Reception339FIGURE 21-23: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Address)340FIGURE 21-24: I2C™ Master Mode Waveform (Reception, 7-bit Address)34121.4.12 Acknowledge Sequence Timing34221.4.13 Stop Condition Timing342FIGURE 21-25: Acknowledge Sequence Waveform342FIGURE 21-26: Stop Condition Receive or Transmit Mode34221.4.14 Sleep Operation34321.4.15 Effects of a Reset34321.4.16 Multi-master Mode34321.4.17 Multi -master Communication, Bus Collision and Bus Arbitration343FIGURE 21-27: Bus Collision Timing for Transmit and Acknowledge343FIGURE 21-28: Bus Collision During Start Condition (SDAx Only)344FIGURE 21-29: Bus Collision During Start Condition (SCLx = 0)345FIGURE 21-30: BRG Reset Due to SDAx Arbitration During Start Condition345FIGURE 21-31: Bus Collision During a Repeated Start Condition (Case 1)346FIGURE 21-32: Bus Collision During Repeated Start Condition (Case 2)346FIGURE 21-33: Bus Collision During a Stop Condition (Case 1)347FIGURE 21-34: Bus Collision During a Stop Condition (Case 2)347TABLE 21-4: Registers Associated with I2C™ Operation34822.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)349Register 22-1: TXSTAx: Transmit Status And Control Register350Register 22-2: RCSTAx: Receive Status And Control Register351Register 22-3: BAUDCONx: Baud Rate Control Register35222.1 Baud Rate Generator (BRG)35322.1.1 Operation in Power-Managed Modes35322.1.2 Sampling353TABLE 22-1: Baud Rate Formulas353EXAMPLE 22-1: Calculating Baud Rate Error354TABLE 22-2: Registers Associated with Baud Rate Generator354TABLE 22-3: Baud Rates for Asynchronous Modes35522.1.3 Auto-Baud Rate Detect357TABLE 22-4: BRG Counter Clock Rates357FIGURE 22-1: Automatic Baud Rate Calculation358FIGURE 22-2: BRG Overflow Sequence35822.2 EUSART Asynchronous Mode35922.2.1 EUSART Asynchronous Transmitter359FIGURE 22-3: EUSART Transmit Block Diagram359FIGURE 22-4: Asynchronous Transmission360FIGURE 22-5: Asynchronous Transmission (Back-to-Back)360TABLE 22-5: Registers Associated with Asynchronous Transmission36122.2.2 EUSART Asynchronous Receiver36222.2.3 Setting Up 9-bit Mode with Address Detect362FIGURE 22-6: EUSART Receive Block Diagram362FIGURE 22-7: Asynchronous Reception363TABLE 22-6: Registers Associated with Asynchronous Reception36322.2.4 Auto-Wake-up on Sync Break Character364FIGURE 22-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation365FIGURE 22-9: Auto-Wake-up Bit (WUE) Timings During Sleep36522.2.5 Break Character Sequence36622.2.6 Receiving A Break Character366FIGURE 22-10: Send Break Character Sequence36622.3 EUSART Synchronous Master Mode36722.3.1 EUSART Synchronous Master Transmission367FIGURE 22-11: Synchronous Transmission367FIGURE 22-12: Synchronous Transmission (Through TXEN)368TABLE 22-7: Registers Associated with Synchronous Master Transmission36822.3.2 EUSART Synchronous Master Reception369FIGURE 22-13: Synchronous Reception (Master Mode, SREN)369TABLE 22-8: Registers Associated with Synchronous Master Reception37022.4 EUSART Synchronous Slave Mode37122.4.1 EUSART Synchronous Slave Transmission371TABLE 22-9: Registers Associated with Synchronous Slave Transmission37122.4.2 EUSART Synchronous Slave Reception372TABLE 22-10: Registers Associated with Synchronous Slave Reception37223.0 12-Bit Analog-to-Digital Converter (A/D) Module37323.1 Differential A/D Converter373FIGURE 23-1: Differential Channel Measurement373FIGURE 23-2: Single Channel Measurement37323.2 A/D Registers37423.2.1 A/D Control Registers374Register 23-1: ADCON0: A/D Control Register 0374Register 23-2: ADCON1: A/D Control Register 1375Register 23-3: ADCON2: A/D Control Register 237623.2.2 A/D Result Registers377FIGURE 23-3: A/D Result Justification377Register 23-4: ADRESH: A/D Result High Byte Register, Left Justified (ADFM = 0)378Register 23-5: ADRESL: A/D Result lOW Byte Register, Left Justified (ADFM = 0)378Register 23-6: ADRESH: A/D Result High Byte Register, Right Justified (ADFM = 1)379Register 23-7: ADRESL: A/D Result Low Byte Register, Right Justified (ADFM = 1)379Register 23-8: ANCON0: A/D Port Configuration Register 0380Register 23-9: ANCON1: A/D Port Configuration Register 1380Register 23-10: ANCON2: A/D Port Configuration Register 2381FIGURE 23-4: A/D Block Diagram382FIGURE 23-5: Analog Input Model38323.3 A/D Acquisition Requirements384EQUATION 23-1: Acquisition Time384EQUATION 23-2: A/D Minimum Charging Time384EQUATION 23-3: Calculating the Minimum Required Acquisition Time38423.4 Selecting and Configuring Automatic Acquisition Time38523.5 Selecting the A/D Conversion Clock385TABLE 23-1: Tad vs. Device Operating Frequencies38523.6 Configuring Analog Port Pins38523.7 A/D Conversions386FIGURE 23-6: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)386FIGURE 23-7: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)38623.8 Use of the Special Event Triggers38723.9 Operation in Power-Managed Modes387TABLE 23-2: Summary of A/D Registers38824.0 Comparator Module38924.1 Registers389FIGURE 24-1: Comparator Simplified Block Diagram389Register 24-1: CMxCON: Comparator Control x Register390Register 24-2: CMSTAT: Comparator Status Register39124.2 Comparator Operation392FIGURE 24-2: Single Comparator39224.3 Comparator Response Time39224.4 Analog Input Connection Considerations392FIGURE 24-3: Comparator Analog Input Model39224.5 Comparator Control and Configuration393TABLE 24-1: Comparator Inputs and Outputs39324.5.1 Comparator Enable and Input selection39324.5.2 Comparator Enable and OUtput Selection393FIGURE 24-4: Comparator Configurations39424.6 Comparator Interrupts395TABLE 24-2: Comparator Interrupt Generation39524.7 Comparator Operation During Sleep39624.8 Effects of a Reset396TABLE 24-3: Registers Associated with Comparator Module39625.0 Comparator Voltage Reference Module39725.1 Configuring the Comparator Voltage Reference397EQUATION 25-1:397Register 25-1: CVRCON: Comparator Voltage Reference Control Register397FIGURE 25-1: Comparator Voltage Reference Block Diagram39825.2 Voltage Reference Accuracy/Error39825.3 Operation During Sleep39825.4 Effects of a Reset39825.5 Connection Considerations398FIGURE 25-2: Comparator Voltage Reference Output Buffer Example399TABLE 25-1: Registers Associated with Comparator Voltage Reference39926.0 High/Low-Voltage Detect (HLVD)401Register 26-1: HLVDCON: High/Low-Voltage Detect Control Register40126.1 Operation402FIGURE 26-1: HLVD Module Block Diagram (with External Input)40226.2 HLVD Setup40326.3 Current Consumption40326.4 HLVD Start-up Time403FIGURE 26-2: Low-Voltage Detect Operation (VDIRMAG = 0)403FIGURE 26-3: High-Voltage Detect Operation (VDIRMAG = 1)40426.5 Applications404FIGURE 26-4: Typical Low-Voltage Detect Application40426.6 Operation During Sleep40526.7 Effects of a Reset405TABLE 26-1: Registers Associated with High/Low-Voltage Detect Module40527.0 Charge Time Measurement Unit (CTMU)407FIGURE 27-1: CTMU Block Diagram40727.1 CTMU Registers408Register 27-1: CTMUCONH: CTMU Control High Register408Register 27-2: CTMUCONL: CTMU Control Low Register409Register 27-3: CTMUICON: CTMU current Control Register41027.2 CTMU Operation41127.2.1 Theory of Operation41127.2.2 Current Source41127.2.3 Edge Selection and Control41127.2.4 Edge Status41127.2.5 Interrupts41227.3 CTMU Module Initialization41227.4 Calibrating the CTMU Module41227.4.1 Current Source Calibration412FIGURE 27-2: CTMU Current Source Calibration Circuit413EXAMPLE 27-1: Setup for CTMU Calibration Routines414EXAMPLE 27-2: Current Calibration Routine41527.4.2 Capacitance Calibration416EXAMPLE 27-3: Capacitance Calibration Routine41727.5 Measuring Capacitance with the CTMU41827.5.1 Absolute Capacitance Measurement41827.5.2 Relative Charge Measurement418EXAMPLE 27-4: Routine for Capacitive Touch Switch41927.6 Measuring Time with the CTMU Module420FIGURE 27-3: Typical Connections and Internal Configuration for Time Measurement42027.7 Creating a Delay with the CTMU Module421FIGURE 27-4: Typical Connections and Internal Configuration for Pulse Delay Generation42127.8 Measuring Temperature Using the CTMU Module422EXAMPLE 27-5: Routine for Temperature Measurement Using Internal Diode42227.9 Operation During Sleep/Idle Modes42327.9.1 Sleep Mode42327.9.2 Idle Mode42327.10 Effects of a Reset on CTMU423TABLE 27-1: Registers Associated with CTMU Module42328.0 Special Features of the CPU42528.1 Configuration Bits425TABLE 28-1: Configuration Bits and Device IDs426Register 28-1: CONFIG1L: Configuration Register 1 lOW (Byte Address 300000h)427Register 28-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)428Register 28-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)429Register 28-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)430Register 28-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)431Register 28-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)431Register 28-7: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)432Register 28-8: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)(2)433Register 28-9: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)(1)434Register 28-10: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)(2)435Register 28-11: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)(2)436Register 28-12: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)(3)437Register 28-13: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)(1)438Register 28-14: DEVID1: Device ID Register 1 for the PIC18F87K90 Family439Register 28-15: DEVID2: Device ID Register 2 for the PIC18F87K90 Family43928.2 Watchdog Timer (WDT)440FIGURE 28-1: WDT Block Diagram44028.2.1 Control Register441Register 28-16: WDTCON: Watchdog Timer Control Register441TABLE 28-2: Summary of Watchdog Timer Registers44128.3 On-Chip Voltage Regulator44228.3.1 Regulator Enable/disable by Hardware442FIGURE 28-2: Connections for the On-chip Regulator44228.3.2 Operation of regulator in Sleep443TABLE 28-3: Sleep Mode Regulator Settings(1)44328.4 Two-Speed Start-up44428.4.1 Special Considerations for Using Two-Speed Start-up444FIGURE 28-3: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)44428.5 Fail-Safe Clock Monitor445FIGURE 28-4: FSCM Block Diagram44528.5.1 FSCM and the Watchdog Timer44528.5.2 Exiting Fail-Safe Operation445FIGURE 28-5: FSCM Timing Diagram44628.5.3 FSCM Interrupts in Power-Managed Modes44628.5.4 POR or Wake From Sleep44628.6 Program Verification and Code Protection447FIGURE 28-6: Code-Protected Program Memory for the PIC18F87K90 Family(1)447TABLE 28-4: Summary of Code Protection Registers44828.6.1 Program Memory Code Protection448FIGURE 28-7: Table Write (WRTn) Disallowed448FIGURE 28-8: External Block Table Read (EBTRn) Disallowed449FIGURE 28-9: External Block Table Read (EBTRn) Allowed44928.6.2 Data EEPROM Code Protection45028.6.3 Configuration Register Protection45028.7 ID Locations45028.8 In-Circuit Serial Programming45028.9 In-Circuit Debugger450TABLE 28-5: Debugger Resources45029.0 Instruction Set Summary45129.1 Standard Instruction Set451TABLE 29-1: Opcode Field Descriptions452FIGURE 29-1: General Format for Instructions453TABLE 29-2: PIC18F87K90 Family Instruction Set45429.1.1 Standard Instruction Set45729.2 Extended Instruction Set49329.2.1 Extended Instruction Syntax493TABLE 29-3: Extensions to the PIC18 Instruction Set49329.2.2 Extended Instruction Set49429.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode49829.2.4 Considerations When Enabling the Extended Instruction Set49829.2.5 Special Considerations with Microchip MPLAB® IDE Tools50030.0 Development Support50131.0 Electrical Characteristics505Absolute Maximum Ratings(†)505FIGURE 31-1: Voltage-frequency Graph, Regulator Enabled (Industrial/Extended)(1)506FIGURE 31-2: Voltage-frequency Graph, Regulator Disabled (Industrial/Extended)(1,2)50631.1 DC Characteristics: Supply Voltage PIC18F87K90 Family (Industrial/Extended)50731.2 DC Characteristics: Power-Down and Supply Current PIC18F87K90 Family (Industrial/Extended)50831.3 DC Characteristics: PIC18F87K90 Family (Industrial/Extended)51931.4 DC Characteristics: CTMU Current Source Specifications520TABLE 31-1: Memory Programming Requirements521TABLE 31-2: Comparator Specifications522TABLE 31-3: Voltage Reference Specifications522TABLE 31-4: Internal Voltage Regulator Specifications52231.5 AC (Timing) Characteristics52331.5.1 Timing Parameter Symbology52331.5.2 Timing Conditions524TABLE 31-5: Temperature and Voltage Specifications – AC524FIGURE 31-3: Load Conditions for Device Timing Specifications52431.5.3 Timing Diagrams and Specifications525FIGURE 31-4: External Clock Timing525TABLE 31-6: External Clock Timing Requirements525TABLE 31-7: PLL Clock Timing Specifications (Vdd = 1.8V to 5.5V)526TABLE 31-8: Internal RC Accuracy (INTOSC)526FIGURE 31-5: CLKO and I/O Timing527TABLE 31-9: CLKO and I/O Timing Requirements527FIGURE 31-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing528FIGURE 31-7: Brown-out Reset Timing528TABLE 31-10: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements529FIGURE 31-8: High/Low-Voltage Detect Characteristics530TABLE 31-11: High/Low-Voltage Detect Characteristics530FIGURE 31-9: Timer0 and Timer1 External Clock Timings531TABLE 31-12: Timer0 and Timer1 External Clock Requirements531FIGURE 31-10: Capture/Compare/PWM Timings (ECCP1, ECCP2 Modules)532TABLE 31-13: Capture/Compare/PWM Requirements (ECCP1, ECCP2 Modules)532FIGURE 31-11: Example SPI Master Mode Timing (CKE = 0)533TABLE 31-14: Example SPI Mode Requirements (Master Mode, Cke = 0)533FIGURE 31-12: Example SPI Master Mode Timing (CKE = 1)534TABLE 31-15: Example SPI Mode Requirements (Master Mode, CKE = 1)534FIGURE 31-13: Example SPI Slave Mode Timing (CKE = 0)535TABLE 31-16: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)535FIGURE 31-14: Example SPI Slave Mode Timing (CKE = 1)536TABLE 31-17: Example SPI Slave Mode Requirements (CKE = 1)536FIGURE 31-15: I2C™ Bus Start/Stop Bits Timing537TABLE 31-18: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)537FIGURE 31-16: I2C™ Bus Data Timing538TABLE 31-19: I2C™ Bus Data Requirements (Slave Mode)538FIGURE 31-17: MSSP I2C™ Bus Start/Stop Bits Timing Waveforms539TABLE 31-20: MSSP I2C™ Bus Start/Stop Bits Requirements539FIGURE 31-18: MSSP I2C™ Bus Data Timing539TABLE 31-21: MSSP I2C™ Bus Data Requirements540FIGURE 31-19: EUSART Synchronous Transmission (Master/Slave) Timing541TABLE 31-22: EUSART/AUSART Synchronous Transmission Requirements541FIGURE 31-20: EUSART/AUSART Synchronous Receive (Master/Slave) Timing541TABLE 31-23: EUSART/AUSART Synchronous Receive Requirements541TABLE 31-24: Ultra Low-Power Wake-up Specifications541TABLE 31-25: A/D Converter Characteristics: PIC18F87K90 Family (Industrial/Extended)542FIGURE 31-21: A/D Conversion Timing543TABLE 31-26: A/D Conversion Requirements54332.0 Packaging Information54532.1 Package Marking Information54532.2 Package Details546Appendix A: Revision History553Revision A (September 2009)553Revision B (April 2010)553Revision C (March 2011)553Revision D (July 2011)553Appendix B: Migration From PIC18F85J90 and PIC18F87J90 to PIC18F87K90553TABLE B-1: Notable Differences Between PIC18F87K90, PIC18F87J90 and PIC18F85J90 Families554INDEX555The Microchip Web Site567Customer Change Notification Service567Customer Support567Reader Response568Product Identification System569Worldwide Sales and Service570サイズ: 4.38MBページ数: 570Language: Englishマニュアルを開く