Microchip Technology ARD00385 사용자 매뉴얼

차례

• Low-Power Features:

  3
• LCD Driver and Keypad Features:

  3
• Peripheral Highlights:

  3
• Special Microcontroller Features:

  4
• Pin Diagrams – PIC18F6XK90

  5
• Pin Diagrams – PIC18F8XK90

  6
• Table of Contents

  7
• 1.0 Device Overview

  9
  • 1.1 Core Features

    9
    • 1.1.1 nanoWatt Technology

      9
    • 1.1.2 Oscillator Options and Features

      9
    • 1.1.3 Memory Options

      9
    • 1.1.4 Extended Instruction Set

      9
    • 1.1.5 Easy Migration

      9
  • 1.2 LCD Driver

    10
  • 1.3 Other Special Features

    10
  • 1.4 Details on Individual Family Members

    10
    • TABLE 1-1: Device Features for the PIC18F6XK90 (64-pin Devices)

      11
    • TABLE 1-2: Device Features for the PIC18F8XK90 (80-pin Devices)

      11
    • FIGURE 1-1: PIC18F6XK90 (64-pin) Block Diagram

      12
    • FIGURE 1-2: PIC18F8XK90 (80-pin) Block Diagram

      13
    • TABLE 1-3: PIC18F6XK90 Pinout I/O Descriptions

      14
    • TABLE 1-4: PIC18F8XK90 Pinout I/O Descriptions

      22
• 2.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers

  35
  • 2.1 Basic Connection Requirements

    35
    • FIGURE 2-1: Recommended Minimum connections

      35
  • 2.2 Power Supply Pins

    36
    • 2.2.1 Decoupling Capacitors

      36
    • 2.2.2 Tank Capacitors

      36
  • 2.3 Master Clear (MCLR) Pin

    36
    • FIGURE 2-2: Example of MCLR Pin Connections

      36
  • 2.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)

    37
    • FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap

      37
    • TABLE 2-1: Suitable Capacitor Equivalents

      37
    • 2.4.1 Considerations for Ceramic Capacitors

      38
      • FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics

        38
  • 2.5 ICSP Pins

    38
  • 2.6 External Oscillator Pins

    39
  • 2.7 Unused I/Os

    39
    • FIGURE 2-5: Suggested Placement of the Oscillator Circuit

      39
• 3.0 Oscillator Configurations

  41
  • 3.1 Oscillator Types

    41
    • TABLE 3-1: HS, EC, XT, LP and RC Modes: Ranges and Settings

      42
    • FIGURE 3-1: PIC18F87K90 Family Clock Diagram

      42
  • 3.2 Control Registers

    43
    • Register 3-1: OSCCON: Oscillator Control Register

      43
    • Register 3-2: OSCCON2: Oscillator Control Register 2

      44
    • Register 3-3: OSCTUNE: Oscillator Tuning Register

      45
  • 3.3 Clock Sources and Oscillator Switching

    45
    • 3.3.1 OSC1/OSC2 Oscillator

      46
    • 3.3.2 Clock Source Selection

      46
    • 3.3.3 Oscillator Transitions

      46
  • 3.4 External Oscillator Modes

    46
    • 3.4.1 Crystal Oscillator/Ceramic Resonators (HS Modes)

      46
      • TABLE 3-2: Capacitor Selection for Ceramic Resonators

        47
      • TABLE 3-3: Capacitor Selection for Crystal Oscillator

        47
      • FIGURE 3-2: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)

        47
  • 3.5 RC Oscillator

    47
    • FIGURE 3-3: RC Oscillator Mode

      48
    • FIGURE 3-4: RCIO Oscillator Mode

      48
    • 3.5.1 External Clock Input (EC Modes)

      48
      • FIGURE 3-5: External Clock Input Operation (EC Configuration)

        48
      • FIGURE 3-6: External Clock Input Operation (HS OSC Configuration)

        48
    • 3.5.2 PLL Frequency Multiplier

      48
      • FIGURE 3-7: PLL Block Diagram

        49
  • 3.6 Internal Oscillator Block

    49
    • 3.6.1 INTIO Modes

      49
      • FIGURE 3-8: INTIO1 Oscillator Mode

        49
      • FIGURE 3-9: INTIO2 Oscillator Mode

        49
    • 3.6.2 INTPLL Modes

      50
    • 3.6.3 Internal Oscillator Output Frequency and Tuning

      50
    • 3.6.4 INTOSC Frequency Drift

      50
  • 3.7 Reference Clock Output

    51
    • Register 3-4: REFOCON: Reference Oscillator Control Register

      51
  • 3.8 Effects of Power-Managed Modes on the Various Clock Sources

    52
  • 3.9 Power-up Delays

    52
    • TABLE 3-4: OSC1 and OSC2 Pin States in Sleep Mode

      52
• 4.0 Power-Managed Modes

  53
  • 4.1 Selecting Power-Managed Modes

    53
    • 4.1.1 Clock Sources

      53
    • 4.1.2 Entering Power-Managed Modes

      53
      • TABLE 4-1: Power-Managed Modes

        53
    • 4.1.3 Clock Transitions and Status Indicators

      54
      • TABLE 4-2: System Clock Indicator

        54
    • 4.1.4 Multiple Sleep Commands

      54
  • 4.2 Run Modes

    54
    • 4.2.1 PRI_RUN Mode

      54
    • 4.2.2 SEC_RUN Mode

      54
      • FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode

        55
      • FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)

        55
    • 4.2.3 RC_RUN Mode

      55
      • TABLE 4-3: Internal Oscillator Frequency Stability Bits

        56
      • FIGURE 4-3: Transition Timing to RC_RUN Mode

        57
      • FIGURE 4-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode

        57
  • 4.3 Sleep Mode

    58
  • 4.4 Idle Modes

    58
    • FIGURE 4-5: Transition Timing for Entry to Sleep Mode

      58
    • FIGURE 4-6: Transition Timing for Wake From Sleep (HSPLL)

      58
    • 4.4.1 PRI_IDLE Mode

      59
    • 4.4.2 SEC_IDLE Mode

      59
      • FIGURE 4-7: Transition Timing for Entry to Idle Mode

        59
      • FIGURE 4-8: Transition Timing for Wake From Idle to Run Mode

        59
    • 4.4.3 RC_IDLE Mode

      60
  • 4.5 Selective Peripheral Module Control

    60
    • Register 4-1: PMD3: Peripheral Module Disable Register 3

      61
    • Register 4-2: PMD2: Peripheral Module Disable Register 2

      62
    • Register 4-3: PMD1: Peripheral Module Disable Register 1

      63
    • Register 4-4: PMD0: Peripheral Module Disable Register 0

      64
  • 4.6 Exiting Idle and Sleep Modes

    65
    • 4.6.1 Exit By Interrupt

      65
    • 4.6.2 Exit By WDT Time-out

      65
    • 4.6.3 Exit By Reset

      65
    • 4.6.4 Exit Without an Oscillator Start-up Delay

      65
  • 4.7 Ultra Low-Power Wake-up

    66
    • EXAMPLE 4-1: Ultra Low-Power Wake-up Initialization

      66
    • FIGURE 4-9: Ultra Low-Power Wake-up Initialization

      66
    • TABLE 4-4: Exit Delay on Wake-up By Reset From Sleep Mode or Any Idle Mode (By Clock Sources)

      67
• 5.0 Reset

  69
  • 5.1 RCON Register

    69
    • FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit

      69
    • Register 5-1: RCON: Reset Control Register

      70
  • 5.2 Master Clear (MCLR)

    71
  • 5.3 Power-on Reset (POR)

    71
  • 5.4 Brown-out Reset (BOR)

    71
    • FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)

      71
    • 5.4.1 Detecting BOR

      71
  • 5.5 Configuration Mismatch (CM)

    72
  • 5.6 Power-up Timer (PWRT)

    72
    • 5.6.1 Time-out Sequence

      72
      • FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)

        72
      • FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1

        73
      • FIGURE 5-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2

        73
      • FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)

        73
  • 5.7 Reset State of Registers

    74
    • TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register

      74
    • TABLE 5-2: Initialization Conditions for All Registers

      75
• 6.0 Memory Organization

  85
  • FIGURE 6-1: Memory Maps for PIC18F87K90 Family Devices

    85
  • 6.1 Program Memory Organization

    86
    • 6.1.1 Hard Memory Vectors

      86
      • FIGURE 6-2: Hard Vector for PIC18F87K90 Family Devices

        86
    • 6.1.2 Program Counter

      87
    • 6.1.3 Return Address Stack

      87
      • FIGURE 6-3: Return Address Stack and Associated Registers

        87
      • Register 6-1: STKPTR: Stack Pointer Register

        88
    • 6.1.4 Fast Register Stack

      89
      • EXAMPLE 6-1: Fast Register Stack Code Example

        89
    • 6.1.5 Look-up Tables in Program Memory

      89
      • EXAMPLE 6-2: Computed GOTO Using an Offset Value

        89
  • 6.2 PIC18 Instruction Cycle

    90
    • 6.2.1 Clocking Scheme

      90
    • 6.2.2 Instruction Flow/Pipelining

      90
      • FIGURE 6-4: Clock/ Instruction Cycle

        90
      • EXAMPLE 6-3: Instruction Pipeline Flow

        90
    • 6.2.3 Instructions in Program Memory

      91
      • FIGURE 6-5: Instructions in Program Memory

        91
    • 6.2.4 Two-Word Instructions

      91
      • EXAMPLE 6-4: Two-Word Instructions

        91
  • 6.3 Data Memory Organization

    92
    • 6.3.1 Bank Select Register

      92
      • FIGURE 6-6: Data Memory Map for PIC18FX5K90 and PIC18FX7K90 Devices

        93
      • FIGURE 6-7: Use of the Bank Select Register (Direct Addressing)

        94
    • 6.3.2 Access Bank

      94
    • 6.3.3 General Purpose Register File

      94
    • 6.3.4 Special Function Registers

      95
      • TABLE 6-1: PIC18F87K90 Family Special Function Register Map(5)

        95
      • TABLE 6-2: PIC18F87K90 Family Register File Summary

        97
    • 6.3.5 STATUS Register

      103
      • Register 6-2: Status Register

        103
  • 6.4 Data Addressing Modes

    104
    • 6.4.1 Inherent and Literal Addressing

      104
    • 6.4.2 Direct Addressing

      104
    • 6.4.3 Indirect Addressing

      104
      • EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing

        104
      • FIGURE 6-8: Indirect Addressing

        105
  • 6.5 Program Memory and the Extended Instruction Set

    106
  • 6.6 Data Memory and the Extended Instruction Set

    107
    • 6.6.1 Indexed Addressing with Literal Offset

      107
    • 6.6.2 Instructions Affected By Indexed Literal Offset Mode

      107
      • FIGURE 6-9: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)

        108
    • 6.6.3 Mapping the Access Bank in Indexed Literal Offset Mode

      109
    • 6.6.4 BSR in Indexed Literal Offset Mode

      109
      • FIGURE 6-10: Remapping the Access Bank with Indexed Literal Offset Addressing

        109
• 7.0 Flash Program Memory

  111
  • 7.1 Table Reads and Table Writes

    111
    • FIGURE 7-1: Table Read Operation

      111
    • FIGURE 7-2: Table Write Operation

      112
  • 7.2 Control Registers

    112
    • 7.2.1 EECON1 and EECON2 Registers

      112
      • Register 7-1: EECON1: EEPROM Control Register 1

        113
    • 7.2.2 TABLAT – Table Latch Register

      114
    • 7.2.3 TBLPTR – Table Pointer Register

      114
    • 7.2.4 Table Pointer Boundaries

      114
      • TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions

        114
      • FIGURE 7-3: Table Pointer Boundaries Based on Operation

        114
  • 7.3 Reading the Flash Program Memory

    115
    • FIGURE 7-4: Reads From Flash Program Memory

      115
    • EXAMPLE 7-1: Reading a Flash Program Memory Word

      115
  • 7.4 Erasing Flash Program Memory

    116
    • 7.4.1 Flash Program Memory Erase Sequence

      116
      • EXAMPLE 7-2: Erasing a Flash Program Memory Row

        116
  • 7.5 Writing to Flash Program Memory

    117
    • FIGURE 7-5: Table Writes to Flash Program Memory

      117
    • 7.5.1 Flash Program Memory Write Sequence

      117
      • EXAMPLE 7-3: Writing to Flash Program Memory

        118
      • EXAMPLE 7-3: Writing to Flash Program Memory (Continued)

        119
    • 7.5.2 Write Verify

      119
    • 7.5.3 Unexpected Termination of Write Operation

      119
    • 7.5.4 Protection Against Spurious Writes

      119
  • 7.6 Flash Program Operation During Code Protection

    119
    • TABLE 7-2: Registers Associated with Program Flash Memory

      119
• 8.0 Data EEPROM Memory

  121
  • 8.1 EEADR and EEADRH Registers

    121
  • 8.2 EECON1 and EECON2 Registers

    121
    • Register 8-1: EECON1: Data EEPROM Control Register 1

      122
  • 8.3 Reading the Data EEPROM Memory

    123
  • 8.4 Writing to the Data EEPROM Memory

    123
  • 8.5 Write Verify

    123
    • EXAMPLE 8-1: Data EEPROM Read

      123
    • EXAMPLE 8-2: Data EEPROM Write

      123
  • 8.6 Operation During Code-Protect

    124
  • 8.7 Protection Against Spurious Write

    124
  • 8.8 Using the Data EEPROM

    124
    • EXAMPLE 8-3: Data EEPROM Refresh Routine

      124
    • TABLE 8-1: Registers Associated with Data EEPROM Memory

      125
• 9.0 8 X 8 Hardware Multiplier

  127
  • 9.1 Introduction

    127
  • 9.2 Operation

    127
    • EXAMPLE 9-1: 8 x 8 Unsigned Multiply Routine

      127
    • EXAMPLE 9-2: 8 x 8 Signed Multiply Routine

      127
    • TABLE 9-1: Performance Comparison for Various Multiply Operations

      127
    • EQUATION 9-1: 16 x 16 Unsigned Multiplication Algorithm

      128
    • EXAMPLE 9-3: 16 x 16 Unsigned Multiply Routine

      128
    • EQUATION 9-2: 16 x 16 Signed Multiplication Algorithm

      128
    • EXAMPLE 9-4: 16 x 16 Signed Multiply Routine

      128
• 10.0 Interrupts

  129
  • FIGURE 10-1: PIC18F87K90 Family Interrupt Logic

    130
  • 10.1 INTCON Registers

    131
    • Register 10-1: INTCON: Interrupt Control Register

      131
    • Register 10-2: INTCON2: Interrupt Control Register 2

      132
    • Register 10-3: INTCON3: Interrupt Control Register 3

      133
  • 10.2 PIR Registers

    134
    • Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1

      134
    • Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2

      135
    • Register 10-6: PIR3: Peripheral Interrupt Request (Flag) Register 3

      136
    • Register 10-7: PIR4: Peripheral Interrupt Flag Register 4

      137
    • Register 10-8: PIR5: Peripheral Interrupt Flag Register 5

      138
    • Register 10-9: PIR6: Peripheral Interrupt Flag Register 6

      139
  • 10.3 PIE Registers

    140
    • Register 10-10: PIE1: Peripheral Interrupt Enable Register 1

      140
    • Register 10-11: PIE2: Peripheral Interrupt Enable Register 2

      141
    • Register 10-12: PIE3: Peripheral Interrupt Enable Register 3

      142
    • Register 10-13: PIE4: Peripheral Interrupt Enable Register 4

      142
    • Register 10-14: PIE5: Peripheral Interrupt Enable Register 5

      143
    • Register 10-15: PIE6: Peripheral Interrupt Enable Register 6

      144
  • 10.4 IPR Registers

    145
    • Register 10-16: IPR1: Peripheral Interrupt Priority Register 1

      145
    • Register 10-17: IPR2: Peripheral Interrupt Priority Register 2

      146
    • Register 10-18: IPR3: Peripheral Interrupt Priority Register 3

      147
    • Register 10-19: IPR4: Peripheral Interrupt Priority Register 4

      147
    • Register 10-20: IPR5: Peripheral Interrupt Priority Register 5

      148
    • Register 10-21: IPR6: Peripheral Interrupt Priority Register 6

      149
  • 10.5 RCON Register

    150
    • Register 10-22: RCON: Reset Control Register

      150
  • 10.6 INTx Pin Interrupts

    151
  • 10.7 TMR0 Interrupt

    151
  • 10.8 PORTB Interrupt-on-Change

    151
  • 10.9 Context Saving During Interrupts

    151
    • EXAMPLE 10-1: Saving STATUS, WREG and BSR Registers in RAM

      151
    • TABLE 10-1: Summary of Registers Associated with Interrupts

      152
• 11.0 I/O Ports

  153
  • FIGURE 11-1: Generic I/O Port Operation

    153
  • 11.1 I/O Port Pin Capabilities

    153
    • 11.1.1 Pin Output Drive

      153
    • 11.1.2 Pull-up Configuration

      153
    • 11.1.3 Open-Drain Outputs

      154
      • FIGURE 11-2: Using the Open-Drain Output (USART Shown as Example)

        154
      • Register 11-1: ODCON1: Peripheral Open-Drain Control Register 1

        154
      • Register 11-2: ODCON2: Peripheral Open-Drain Control Register 2

        155
      • Register 11-3: ODCON3: Peripheral Open-Drain Control Register 3

        156
    • 11.1.4 Analog and Digital Ports

      156
  • 11.2 PORTA, TRISA and LATA Registers

    157
    • EXAMPLE 11-1: Initializing PORTA

      157
    • TABLE 11-1: PORTA Functions

      158
    • TABLE 11-2: Summary of Registers Associated with PORTA

      159
  • 11.3 PORTB, TRISB and LATB Registers

    160
    • EXAMPLE 11-2: Initializing PORTB

      160
    • TABLE 11-3: PORTB Functions

      161
    • TABLE 11-4: Summary of Registers Associated with PORTB

      162
  • 11.4 PORTC, TRISC and LATC Registers

    163
    • EXAMPLE 11-3: Initializing PORTC

      163
    • TABLE 11-5: PORTC Functions

      164
    • TABLE 11-6: Summary of Registers Associated with PORTC

      165
  • 11.5 PORTD, TRISD and LATD Registers

    166
    • EXAMPLE 11-4: Initializing PORTD

      166
    • TABLE 11-7: PORTD Functions

      167
    • TABLE 11-8: Summary of Registers Associated with PORTD

      168
  • 11.6 PORTE, TRISE and LATE Registers

    169
    • TABLE 11-9: PORTE Pins Available in Different LCD Drive Configurations(1)

      169
    • EXAMPLE 11-5: Initializing PORTE

      169
    • TABLE 11-10: PORTE Functions

      170
    • TABLE 11-11: Summary of Registers Associated with PORTE

      171
  • 11.7 PORTF, LATF and TRISF Registers

    172
    • EXAMPLE 11-6: Initializing PORTF

      172
    • TABLE 11-12: PORTF Functions

      173
    • TABLE 11-13: Summary of Registers Associated with PORTF

      174
  • 11.8 PORTG, TRISG and LATG Registers

    175
    • EXAMPLE 11-7: Initializing PORTG

      175
    • TABLE 11-14: PORTG Functions

      175
    • TABLE 11-15: Summary of Registers Associated with PORTG

      176
  • 11.9 PORTH, LATH and TRISH Registers

    177
    • EXAMPLE 11-8: Initializing PORTH

      177
    • TABLE 11-16: PORTH Functions

      178
    • TABLE 11-17: Summary of Registers Associated with PORTH

      179
  • 11.10 PORTJ, TRISJ and LATJ Registers

    180
    • EXAMPLE 11-9: Initializing PORTJ

      180
    • TABLE 11-18: PORTJ Functions

      181
    • TABLE 11-19: Summary of Registers Associated with PORTJ

      181
• 12.0 Timer0 Module

  183
  • Register 12-1: T0CON: Timer0 Control Register

    183
  • 12.1 Timer0 Operation

    184
  • 12.2 Timer0 Reads and Writes in 16-Bit Mode

    184
    • FIGURE 12-1: Timer0 Block Diagram (8-bit Mode)

      184
    • FIGURE 12-2: Timer0 Block Diagram (16-bit Mode)

      184
  • 12.3 Prescaler

    185
    • 12.3.1 Switching Prescaler Assignment

      185
  • 12.4 Timer0 Interrupt

    185
    • TABLE 12-1: Registers Associated with Timer0

      185
• 13.0 Timer1 Module

  187
  • Register 13-1: T1CON: Timer1 Control Register

    187
  • 13.1 Timer1 Gate Control Register

    188
    • Register 13-2: T1GCON: Timer1 Gate Control Register(1)

      188
  • 13.2 Timer1 Operation

    189
  • 13.3 Clock Source Selection

    189
    • 13.3.1 INTERNAL CLOCK SOURCE

      189
    • 13.3.2 EXTERNAL CLOCK SOURCE

      189
      • TABLE 13-1: Timer1 Clock Source Selection

        189
      • FIGURE 13-1: Timer1 Block Diagram

        190
  • 13.4 Timer1 16-Bit Read/Write Mode

    191
  • 13.5 SOSC Oscillator

    191
    • FIGURE 13-2: External Components for the SOSC Oscillator

      191
    • TABLE 13-2: Capacitor Selection for the Timer Oscillator(2,3,4,5)

      191
    • 13.5.1 Using SOSC as a Clock Source

      192
    • 13.5.2 SOSC Oscillator Layout Considerations

      192
      • FIGURE 13-3: Oscillator Circuit with Grounded Guard Ring

        192
  • 13.6 Timer1 Interrupt

    192
  • 13.7 Resetting Timer1 Using the ECCP Special Event Trigger

    193
  • 13.8 Timer1 Gate

    193
    • 13.8.1 TIMER1 GATE COUNT ENABLE

      193
      • TABLE 13-3: TIMER1 GATE ENABLE SELECTIONS

        193
      • FIGURE 13-4: Timer1 Gate Count Enable Mode

        193
    • 13.8.2 TIMER1 GATE SOURCE SELECTION

      194
      • TABLE 13-4: TIMER1 GATE SOURCES

        194
    • 13.8.3 TIMER1 GATE TOGGLE MODE

      195
      • FIGURE 13-5: Timer1 Gate Toggle Mode

        195
    • 13.8.4 TIMER1 GATE SINGLE PULSE MODE

      196
    • 13.8.5 TIMER1 GATE VALUE STATUS

      196
      • FIGURE 13-6: Timer1 Gate Single Pulse Mode

        196
      • FIGURE 13-7: Timer1 Gate Single Pulse and Toggle Combined Mode

        197
      • TABLE 13-5: Registers Associated with Timer1 as a Timer/Counter

        197
• 14.0 Timer2 Module

  199
  • 14.1 Timer2 Operation

    199
    • Register 14-1: T2CON: Timer2 Control Register

      199
  • 14.2 Timer2 Interrupt

    200
  • 14.3 Timer2 Output

    200
    • FIGURE 14-1: Timer2 Block Diagram

      200
    • TABLE 14-1: Registers Associated with Timer2 as a Timer/Counter

      200
• 15.0 Timer3/5/7 Modules

  201
  • Register 15-1: TxCON: Timer3/5/7 Control Register

    202
  • 15.1 Timer3/5/7 Gate Control Register

    203
    • Register 15-2: TxGCON: Timer3/5/7 Gate Control Register(1)

      203
    • Register 15-3: OSCCON2: Oscillator Control Register 2

      204
  • 15.2 Timer3/5/7 Operation

    205
    • FIGURE 15-1: Timer3/5/7 Block Diagram

      205
  • 15.3 Timer3/5/7 16-Bit Read/Write Mode

    206
  • 15.4 Using the SOSC Oscillator as the Timer3/5/7 Clock Source

    206
  • 15.5 Timer3/5/7 Gates

    206
    • 15.5.1 TIMER3/5/7 GATE COUNT ENABLE

      206
      • TABLE 15-1: TIMER3/5/7 GATE ENABLE SELECTIONS

        206
      • FIGURE 15-2: Timer3/5/7 Gate Count Enable Mode

        206
    • 15.5.2 TIMER3/5/7 GATE SOURCE SELECTION

      207
      • TABLE 15-2: TIMER3/5/7 GATE SOURCES

        207
    • 15.5.3 TIMER3/5/7 GATE TOGGLE MODE

      207
      • FIGURE 15-3: Timer3/5/7 Gate Toggle Mode

        207
    • 15.5.4 TIMER3/5/7 GATE SINGLE PULSE MODE

      208
      • FIGURE 15-4: Timer3/5/7 Gate Single Pulse Mode

        208
      • FIGURE 15-5: Timer3/5/7 Gate Single Pulse and Toggle Combined Mode

        209
    • 15.5.5 TIMER3/5/7 GATE VALUE STATUS

      209
    • 15.5.6 TIMER3/5/7 GATE EVENT INTERRUPT

      209
  • 15.6 Timer3/5/7 Interrupt

    210
    • TABLE 15-3: Timer3/5/7 Interrupt Flag Bits

      210
    • TABLE 15-4: Timer3/5/7 Interrupt Enable Bits

      210
  • 15.7 Resetting Timer3/5/7 Using the ECCP Special Event Trigger

    210
    • TABLE 15-5: Registers Associated with Timer3/5/7 as a Timer/Counter

      211
• 16.0 Timer4/6/8/10/12 Modules

  213
  • 16.1 Timer4/6/8/10/12 Operation

    213
    • TABLE 16-1: Timer4/6/8/10/12 Flag Bits

      213
    • TABLE 16-2: Timer4/6/8/10/12 Interrupt Enable Bits

      213
    • Register 16-1: TxCON: Timer4/6/8/10/12 Control Register

      214
  • 16.2 Timer4/6/8/10/12 Interrupt

    215
  • 16.3 Output of TMRx

    215
    • FIGURE 16-1: Timer4/6/8/10/12 Block Diagram

      215
    • TABLE 16-3: Registers Associated with Timer4/6/8/10/12 as a Timer/Counter

      215
• 17.0 Real-Time Clock and Calendar (RTCC)

  217
  • FIGURE 17-1: RTCC Block Diagram

    217
  • 17.1 RTCC Module Registers

    218
  • RTCC Control Registers

    218
  • RTCC Value Registers

    218
  • Alarm Value Registers

    218
    • 17.1.1 RTCC Control Registers

      219
      • Register 17-1: RTCCFG: RTCC Configuration Register(1)

        219
      • Register 17-2: RTCCAL: RTCC Calibration Register

        220
      • Register 17-3: PADCFG1: Pad Configuration Register

        220
      • Register 17-4: ALRMCFG: Alarm Configuration Register

        221
      • Register 17-5: ALRMRPT: Alarm Repeat Register

        222
    • 17.1.2 RTCVALH and RTCVALL Register Mappings

      222
      • Register 17-6: Reserved Register

        222
      • Register 17-7: Year: Year Value Register(1)

        223
      • Register 17-8: MontH: Month Value Register(1)

        223
      • Register 17-9: Day: Day Value Register(1)

        224
      • Register 17-10: Weekday: Weekday Value Register(1)

        224
      • Register 17-11: Hour: Hour Value Register(1)

        225
      • Register 17-12: MINUTE: Minute Value Register

        225
      • Register 17-13: SECOND: Second Value Register

        225
    • 17.1.3 ALRMVALH and ALRMVALL Register Mappings

      226
      • Register 17-14: ALRMMNTH: Alarm Month Value Register(1)

        226
      • Register 17-15: ALRMDAY: Alarm Day Value Register(1)

        226
      • Register 17-16: ALRMWd: Alarm Weekday Value Register(1)

        227
      • Register 17-17: ALRMHr: Alarm Hours Value Register(1)

        227
      • Register 17-18: ALRMMIN: Alarm Minutes Value Register

        228
      • Register 17-19: ALRMSEC: Alarm Seconds Value Register

        228
    • 17.1.4 RTCEN Bit Write

      229
  • 17.2 Operation

    229
    • 17.2.1 Register Interface

      229
      • FIGURE 17-2: Timer Digit Format

        229
      • FIGURE 17-3: Alarm Digit Format

        229
    • 17.2.2 Clock Source

      230
      • FIGURE 17-4: Clock Source Multiplexing

        230
    • 17.2.3 Digit Carry Rules

      230
      • TABLE 17-1: Day of Week Schedule

        230
      • TABLE 17-2: Day-to-Month Rollover Schedule

        230
    • 17.2.4 Leap Year

      231
    • 17.2.5 General Functionality

      231
    • 17.2.6 Safety Window for Register Reads and Writes

      231
    • 17.2.7 Write Lock

      231
      • EXAMPLE 17-1: Setting the RTCWREN Bit

        231
    • 17.2.8 Register Mapping

      231
      • TABLE 17-3: RTCVALH and RTCVALL Register Mapping

        231
      • TABLE 17-4: ALRMVAL Register Mapping

        232
    • 17.2.9 Calibration

      232
      • EQUATION 17-1: Converting Error Clock Pulses

        232
  • 17.3 Alarm

    232
    • 17.3.1 Configuring the Alarm

      232
      • FIGURE 17-5: Alarm Mask Settings

        233
    • 17.3.2 Alarm Interrupt

      233
      • FIGURE 17-6: Timer Pulse Generation

        234
  • 17.4 Sleep Mode

    234
  • 17.5 Reset

    234
    • 17.5.1 Device Reset

      234
    • 17.5.2 Power-on Reset (POR)

      234
  • 17.6 Register Maps

    235
    • TABLE 17-5: RTCC Control Registers

      235
    • TABLE 17-6: RTCC Value Registers

      235
    • TABLE 17-7: Alarm Value Registers

      235
• 18.0 Capture/Compare/PWM (CCP) Modules

  237
  • Register 18-1: CCPxCON: CCPx Control Register (CCP4-CCP10 Modules)(1)

    237
  • Register 18-2: CCPTMRS1: CCPx Timer Select Register 1

    238
  • Register 18-3: CCPTMRS2: CCPx Timer Select Register 2

    239
  • Register 18-4: CCPRxL: CCPx Period Low Byte Register

    240
  • Register 18-5: CCPRxH: CCPx Period High Byte Register

    240
  • 18.1 CCP Module Configuration

    241
    • 18.1.1 CCP Modules and Timer Resources

      241
      • TABLE 18-1: CCP Mode – Timer Resource

        241
      • TABLE 18-2: Timer Assignments for CCP Modules 4, 5, 6 and 7

        241
      • TABLE 18-3: Timer Assignments for CCP Modules 8, 9 and 10

        241
    • 18.1.2 Open-Drain Output Option

      242
    • 18.1.3 Pin Assignment For CCP6, CCP7, CCP8 and CCP9

      242
      • TABLE 18-4: CCP Pin Assignment

        242
  • 18.2 Capture Mode

    242
    • 18.2.1 CCP Pin Configuration

      242
    • 18.2.2 Timer1/3/5/7 Mode Selection

      242
      • FIGURE 18-1: Capture Mode Operation Block Diagram

        243
    • 18.2.3 Software Interrupt

      243
    • 18.2.4 CCP Prescaler

      243
      • EXAMPLE 18-1: Changing Between Capture Prescalers

        243
  • 18.3 Compare Mode

    244
    • 18.3.1 CCP Pin Configuration

      244
    • 18.3.2 Timer1/3/5/7 Mode Selection

      244
    • 18.3.3 Software Interrupt Mode

      244
    • 18.3.4 Special Event Trigger

      244
      • FIGURE 18-2: Compare Mode Operation Block Diagram

        245
      • TABLE 18-5: Registers Associated with Capture, Compare, Timer1/3/5/7

        246
  • 18.4 PWM Mode

    247
    • FIGURE 18-3: Simplified PWM Block Diagram

      247
    • FIGURE 18-4: PWM Output

      248
    • 18.4.1 PWM Period

      248
      • EQUATION 18-1:

        248
    • 18.4.2 PWM Duty Cycle

      248
      • EQUATION 18-2:

        248
      • EQUATION 18-3:

        248
      • TABLE 18-6: Example PWM Frequencies and Resolutions at 40 MHz

        248
    • 18.4.3 Setup for PWM Operation

      249
      • TABLE 18-7: Registers Associated with PWM and Timers

        249
• 19.0 Enhanced Capture/Compare/PWM (ECCP) Module

  251
  • Register 19-1: CCPxCON: Enhanced Capture/Compare/PWM x Control

    252
  • Register 19-2: CCPTMRS0: CCP Timer Select 0 Register

    253
  • 19.1 ECCP Outputs and Configuration

    254
    • 19.1.1 ECCP Module and Timer Resources

      254
      • TABLE 19-1: ECCP Mode – Timer Resource

        254
    • 19.1.2 ECCP Pin Assignment

      254
  • 19.2 Capture Mode

    255
    • TABLE 19-2: ECCP1/2/3 Interrupt Flag Bits

      255
    • 19.2.1 ECCP Pin Configuration

      255
    • 19.2.2 Timer1/Timer3 Mode Selection

      255
    • 19.2.3 Software Interrupt

      255
    • 19.2.4 ECCP Prescaler

      255
      • EXAMPLE 19-1: Changing Between Capture Prescalers

        255
      • FIGURE 19-1: Capture Mode Operation Block Diagram

        255
  • 19.3 Compare Mode

    256
    • 19.3.1 ECCP Pin Configuration

      256
    • 19.3.2 Timer1/Timer3 Mode Selection

      256
    • 19.3.3 Software Interrupt Mode

      256
    • 19.3.4 Special Event Trigger

      256
      • FIGURE 19-2: Compare Mode Operation Block Diagram

        256
  • 19.4 PWM (Enhanced Mode)

    257
    • FIGURE 19-3: Example Simplified Block Diagram of the Enhanced PWM Mode

      257
    • TABLE 19-3: Example Pin Assignments for Various PWM Enhanced Modes

      258
    • FIGURE 19-4: Example PWM (enhanced Mode) Output Relationships (Active-High State)

      258
    • FIGURE 19-5: Example Enhanced PWM Output Relationships (Active-Low State)

      259
    • 19.4.1 Half-Bridge Mode

      260
      • FIGURE 19-6: Example of Half-Bridge PWM Output

        260
      • FIGURE 19-7: Example of Half-Bridge Applications

        260
    • 19.4.2 Full-Bridge Mode

      261
      • FIGURE 19-8: Example of Full-Bridge Application

        261
      • FIGURE 19-9: Example of Full-Bridge PWM Output

        262
      • FIGURE 19-10: Example of PWM Direction Change

        263
      • FIGURE 19-11: Example of PWM Direction Change at Near 100% Duty Cycle(1)

        264
    • 19.4.3 Start-up Considerations

      264
    • 19.4.4 Enhanced PWM Auto-shutdown mode

      264
      • Register 19-3: ECCPxAS: ECCPx Auto-Shutdown Control Register

        265
      • FIGURE 19-12: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)

        266
    • 19.4.5 Auto-Restart Mode

      266
      • FIGURE 19-13: PWM Auto-shutdown With Auto-Restart Enabled (PxRSEN = 1)

        266
    • 19.4.6 Programmable Dead-Band Delay Mode

      267
      • FIGURE 19-14: Example of Half-Bridge PWM Output

        267
      • FIGURE 19-15: Example of Half-Bridge Applications

        267
      • Register 19-4: ECCPxDEL: Enhanced PWM Control Register

        268
    • 19.4.7 Pulse Steering Mode

      268
      • Register 19-5: PSTRxCON: Pulse Steering Control(1)

        269
      • FIGURE 19-16: Simplified Steering Block Diagram

        270
      • FIGURE 19-17: Example of Steering Event at End of Instruction (STRSYNC = 0)

        270
      • FIGURE 19-18: Example of Steering Event at Beginning of Instruction (STRSYNC = 1)

        270
    • 19.4.8 Operation in Power-Managed Modes

      271
    • 19.4.9 Effects of a Reset

      271
      • TABLE 19-4: Registers Associated with ECCP1/2/3 Module and Timer1/2/3/4/6/8/10/12

        272
• 20.0 Liquid Crystal Display (LCD) Driver Module

  273
  • FIGURE 20-1: LCD Driver Module Block Diagram

    273
  • 20.1 LCD Registers

    274
    • Register 20-1: LCDCON: LCD Control Register

      274
    • Register 20-2: LCDPS: LCD Phase Register

      275
    • Register 20-3: LCDREF: LCD Reference Voltage Control Register

      276
    • Register 20-4: LCDRL: LCD Reference Ladder Control Register

      277
    • TABLE 20-1: LCDSE Registers and Associated Segments

      278
    • Register 20-5: LCDSEx: LCD Segmentx Enable Register

      278
    • TABLE 20-2: LCDDATA Registers and Bits for Segment and COM Combinations

      279
    • Register 20-6: LCDDATAx: LCD Datax Register

      279
  • 20.2 LCD Clock Source Selection

    280
    • 20.2.1 LCD Prescaler

      280
      • FIGURE 20-2: LCD Clock Generation

        280
  • 20.3 LCD Bias Types

    281
    • 20.3.1 External resistor biasing

      281
      • FIGURE 20-3: LCD BIAS External Resistor Ladder Connection diagram

        281
    • 20.3.2 Internal resistor biasing

      282
      • TABLE 20-3: Internal Resistance Ladder Power Modes

        282
      • FIGURE 20-4: LCD BIAS Internal Resistor Ladder Connection diagram

        282
      • FIGURE 20-5: LCD REFERENCE LADDER POWER MODE SWITCHING DIAGRAM

        283
      • FIGURE 20-6: INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM

        284
  • 20.4 LCD Multiplex Types

    285
    • TABLE 20-4: PORTE<6:4> Function

      285
  • 20.5 Segment Enables

    285
  • 20.6 Pixel Control

    285
  • 20.7 LCD Frame Frequency

    286
    • TABLE 20-5: Frame Frequency Formulas

      286
    • TABLE 20-6: Approximate Frame Frequency (in Hz) Using Fosc at 32 MHz, Timer1 at 32.768 kHz or INTRC Osc

      286
  • 20.8 LCD Waveform Generation

    286
    • FIGURE 20-7: Type-A/Type-B Waveforms in Static Drive

      287
    • FIGURE 20-8: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive

      288
    • FIGURE 20-9: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive

      289
    • FIGURE 20-10: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive

      290
    • FIGURE 20-11: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive

      291
    • FIGURE 20-12: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive

      292
    • FIGURE 20-13: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive

      293
    • FIGURE 20-14: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive

      294
    • FIGURE 20-15: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive

      295
    • FIGURE 20-16: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive

      296
    • FIGURE 20-17: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive

      297
  • 20.9 LCD Interrupts

    298
    • FIGURE 20-18: Example Waveforms and Interrupt Timing in Quarter Duty Cycle Drive

      298
  • 20.10 Operation During Sleep

    299
    • FIGURE 20-19: Sleep Entry/Exit When SLPEN = 1 or CS<1:0> = 00

      299
  • 20.11 Configuring the LCD Module

    300
    • TABLE 20-7: Registers Associated with LCD Operation

      301
• 21.0 Master Synchronous Serial Port (MSSP) Module

  303
  • 21.1 Master SSP (MSSP) Module Overview

    303
  • 21.2 Control Registers

    303
  • 21.3 SPI Mode

    303
    • FIGURE 21-1: MSSPx Block Diagram (SPI Mode)

      303
    • 21.3.1 Registers

      304
      • Register 21-1: SSPxSTAT: MSSPx Status Register (SPI Mode)

        304
      • Register 21-2: SSPxCON1: MSSPx Control Register 1 (SPI Mode)

        305
    • 21.3.2 Operation

      306
    • 21.3.3 OPEN-DRAIN OUTPUT OPTION

      306
      • EXAMPLE 21-1: Loading the SSP1BUF (SSP1SR) Register

        306
    • 21.3.4 Enabling SPI I/O

      307
    • 21.3.5 Typical Connection

      307
      • FIGURE 21-2: SPI Master/Slave Connection

        307
    • 21.3.6 Master Mode

      308
      • FIGURE 21-3: SPI Mode Waveform (Master Mode)

        308
    • 21.3.7 Slave Mode

      309
    • 21.3.8 Slave Select Synchronization

      309
      • FIGURE 21-4: Slave Synchronization Waveform

        309
      • FIGURE 21-5: SPI Mode Waveform (Slave Mode with CKE = 0)

        310
      • FIGURE 21-6: SPI Mode Waveform (Slave Mode with CKE = 1)

        310
    • 21.3.9 Operation in Power-Managed Modes

      311
    • 21.3.10 Effects of a Reset

      311
    • 21.3.11 Bus Mode Compatibility

      311
      • TABLE 21-1: SPI Bus Modes

        311
    • 21.3.12 SPI Clock Speed and Module Interactions

      311
      • TABLE 21-2: Registers Associated with SPI Operation

        312
  • 21.4 I2C™ Mode

    313
    • FIGURE 21-7: MSSPx Block Diagram (I2C™ Mode)

      313
    • 21.4.1 Registers

      313
      • Register 21-3: SSPxSTAT: MSSPx Status Register (I2C™ Mode)

        314
      • Register 21-4: SSPxCON1: MSSPx Control Register 1 (I2C™ Mode)

        315
      • Register 21-5: SSPxCON2: MSSPx Control Register 2 (I2C™ Master Mode)

        316
      • Register 21-6: SSPxCON2: MSSPx Control Register 2 (I2C™ Slave Mode)

        317
      • Register 21-7: SSPxMSK: I2C™ Slave Address Mask Register (7-bit Masking Mode)(1)

        317
    • 21.4.2 Operation

      318
    • 21.4.3 Slave Mode

      318
      • EXAMPLE 21-2: Address Masking Examples in 5-bit Masking Mode

        319
      • EXAMPLE 21-3: Address Masking Examples in 7-Bit Masking Mode

        320
      • FIGURE 21-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)

        322
      • FIGURE 21-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Address)

        323
      • FIGURE 21-10: I2C™ Slave Mode Timing (Transmission, 7-bit Address)

        324
      • FIGURE 21-11: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Address)

        325
      • FIGURE 21-12: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)

        326
      • FIGURE 21-13: I2C™ Slave Mode Timing (Transmission, 10-bit Address)

        327
    • 21.4.4 Clock Stretching

      328
      • FIGURE 21-14: Clock Synchronization Timing

        329
      • FIGURE 21-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)

        330
      • FIGURE 21-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)

        331
    • 21.4.5 General Call Address Support

      332
      • FIGURE 21-17: Slave Mode General Call Address Sequence (7 or 10-bit Addressing Mode)

        332
    • 21.4.6 Master Mode

      333
      • FIGURE 21-18: MSSP Block Diagram (I2C™ Master Mode)

        333
    • 21.4.7 Baud Rate

      335
      • FIGURE 21-19: Baud Rate Generator Block Diagram

        335
      • TABLE 21-3: I2C™ Clock Rate w/BRG

        335
      • FIGURE 21-20: Baud Rate Generator Timing with Clock Arbitration

        336
    • 21.4.8 I2C™ Master Mode Start Condition Timing

      337
      • FIGURE 21-21: First Start Bit Timing

        337
    • 21.4.9 I2C™ Master Mode Repeated Start Condition Timing

      338
      • FIGURE 21-22: Repeated Start Condition Waveform

        338
    • 21.4.10 I2C™ Master Mode Transmission

      339
    • 21.4.11 I2C Master Mode Reception

      339
      • FIGURE 21-23: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Address)

        340
      • FIGURE 21-24: I2C™ Master Mode Waveform (Reception, 7-bit Address)

        341
    • 21.4.12 Acknowledge Sequence Timing

      342
    • 21.4.13 Stop Condition Timing

      342
      • FIGURE 21-25: Acknowledge Sequence Waveform

        342
      • FIGURE 21-26: Stop Condition Receive or Transmit Mode

        342
    • 21.4.14 Sleep Operation

      343
    • 21.4.15 Effects of a Reset

      343
    • 21.4.16 Multi-master Mode

      343
    • 21.4.17 Multi -master Communication, Bus Collision and Bus Arbitration

      343
      • FIGURE 21-27: Bus Collision Timing for Transmit and Acknowledge

        343
      • FIGURE 21-28: Bus Collision During Start Condition (SDAx Only)

        344
      • FIGURE 21-29: Bus Collision During Start Condition (SCLx = 0)

        345
      • FIGURE 21-30: BRG Reset Due to SDAx Arbitration During Start Condition

        345
      • FIGURE 21-31: Bus Collision During a Repeated Start Condition (Case 1)

        346
      • FIGURE 21-32: Bus Collision During Repeated Start Condition (Case 2)

        346
      • FIGURE 21-33: Bus Collision During a Stop Condition (Case 1)

        347
      • FIGURE 21-34: Bus Collision During a Stop Condition (Case 2)

        347
      • TABLE 21-4: Registers Associated with I2C™ Operation

        348
• 22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

  349
  • Register 22-1: TXSTAx: Transmit Status And Control Register

    350
  • Register 22-2: RCSTAx: Receive Status And Control Register

    351
  • Register 22-3: BAUDCONx: Baud Rate Control Register

    352
  • 22.1 Baud Rate Generator (BRG)

    353
    • 22.1.1 Operation in Power-Managed Modes

      353
    • 22.1.2 Sampling

      353
      • TABLE 22-1: Baud Rate Formulas

        353
      • EXAMPLE 22-1: Calculating Baud Rate Error

        354
      • TABLE 22-2: Registers Associated with Baud Rate Generator

        354
      • TABLE 22-3: Baud Rates for Asynchronous Modes

        355
    • 22.1.3 Auto-Baud Rate Detect

      357
      • TABLE 22-4: BRG Counter Clock Rates

        357
      • FIGURE 22-1: Automatic Baud Rate Calculation

        358
      • FIGURE 22-2: BRG Overflow Sequence

        358
  • 22.2 EUSART Asynchronous Mode

    359
    • 22.2.1 EUSART Asynchronous Transmitter

      359
      • FIGURE 22-3: EUSART Transmit Block Diagram

        359
      • FIGURE 22-4: Asynchronous Transmission

        360
      • FIGURE 22-5: Asynchronous Transmission (Back-to-Back)

        360
      • TABLE 22-5: Registers Associated with Asynchronous Transmission

        361
    • 22.2.2 EUSART Asynchronous Receiver

      362
    • 22.2.3 Setting Up 9-bit Mode with Address Detect

      362
      • FIGURE 22-6: EUSART Receive Block Diagram

        362
      • FIGURE 22-7: Asynchronous Reception

        363
      • TABLE 22-6: Registers Associated with Asynchronous Reception

        363
    • 22.2.4 Auto-Wake-up on Sync Break Character

      364
      • FIGURE 22-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation

        365
      • FIGURE 22-9: Auto-Wake-up Bit (WUE) Timings During Sleep

        365
    • 22.2.5 Break Character Sequence

      366
    • 22.2.6 Receiving A Break Character

      366
      • FIGURE 22-10: Send Break Character Sequence

        366
  • 22.3 EUSART Synchronous Master Mode

    367
    • 22.3.1 EUSART Synchronous Master Transmission

      367
      • FIGURE 22-11: Synchronous Transmission

        367
      • FIGURE 22-12: Synchronous Transmission (Through TXEN)

        368
      • TABLE 22-7: Registers Associated with Synchronous Master Transmission

        368
    • 22.3.2 EUSART Synchronous Master Reception

      369
      • FIGURE 22-13: Synchronous Reception (Master Mode, SREN)

        369
      • TABLE 22-8: Registers Associated with Synchronous Master Reception

        370
  • 22.4 EUSART Synchronous Slave Mode

    371
    • 22.4.1 EUSART Synchronous Slave Transmission

      371
      • TABLE 22-9: Registers Associated with Synchronous Slave Transmission

        371
    • 22.4.2 EUSART Synchronous Slave Reception

      372
      • TABLE 22-10: Registers Associated with Synchronous Slave Reception

        372
• 23.0 12-Bit Analog-to-Digital Converter (A/D) Module

  373
  • 23.1 Differential A/D Converter

    373
    • FIGURE 23-1: Differential Channel Measurement

      373
    • FIGURE 23-2: Single Channel Measurement

      373
  • 23.2 A/D Registers

    374
    • 23.2.1 A/D Control Registers

      374
      • Register 23-1: ADCON0: A/D Control Register 0

        374
      • Register 23-2: ADCON1: A/D Control Register 1

        375
      • Register 23-3: ADCON2: A/D Control Register 2

        376
    • 23.2.2 A/D Result Registers

      377
      • FIGURE 23-3: A/D Result Justification

        377
      • Register 23-4: ADRESH: A/D Result High Byte Register, Left Justified (ADFM = 0)

        378
      • Register 23-5: ADRESL: A/D Result lOW Byte Register, Left Justified (ADFM = 0)

        378
      • Register 23-6: ADRESH: A/D Result High Byte Register, Right Justified (ADFM = 1)

        379
      • Register 23-7: ADRESL: A/D Result Low Byte Register, Right Justified (ADFM = 1)

        379
      • Register 23-8: ANCON0: A/D Port Configuration Register 0

        380
      • Register 23-9: ANCON1: A/D Port Configuration Register 1

        380
      • Register 23-10: ANCON2: A/D Port Configuration Register 2

        381
      • FIGURE 23-4: A/D Block Diagram

        382
      • FIGURE 23-5: Analog Input Model

        383
  • 23.3 A/D Acquisition Requirements

    384
    • EQUATION 23-1: Acquisition Time

      384
    • EQUATION 23-2: A/D Minimum Charging Time

      384
    • EQUATION 23-3: Calculating the Minimum Required Acquisition Time

      384
  • 23.4 Selecting and Configuring Automatic Acquisition Time

    385
  • 23.5 Selecting the A/D Conversion Clock

    385
    • TABLE 23-1: Tad vs. Device Operating Frequencies

      385
  • 23.6 Configuring Analog Port Pins

    385
  • 23.7 A/D Conversions

    386
    • FIGURE 23-6: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)

      386
    • FIGURE 23-7: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)

      386
  • 23.8 Use of the Special Event Triggers

    387
  • 23.9 Operation in Power-Managed Modes

    387
    • TABLE 23-2: Summary of A/D Registers

      388
• 24.0 Comparator Module

  389
  • 24.1 Registers

    389
    • FIGURE 24-1: Comparator Simplified Block Diagram

      389
    • Register 24-1: CMxCON: Comparator Control x Register

      390
    • Register 24-2: CMSTAT: Comparator Status Register

      391
  • 24.2 Comparator Operation

    392
    • FIGURE 24-2: Single Comparator

      392
  • 24.3 Comparator Response Time

    392
  • 24.4 Analog Input Connection Considerations

    392
    • FIGURE 24-3: Comparator Analog Input Model

      392
  • 24.5 Comparator Control and Configuration

    393
    • TABLE 24-1: Comparator Inputs and Outputs

      393
    • 24.5.1 Comparator Enable and Input selection

      393
    • 24.5.2 Comparator Enable and OUtput Selection

      393
      • FIGURE 24-4: Comparator Configurations

        394
  • 24.6 Comparator Interrupts

    395
    • TABLE 24-2: Comparator Interrupt Generation

      395
  • 24.7 Comparator Operation During Sleep

    396
  • 24.8 Effects of a Reset

    396
    • TABLE 24-3: Registers Associated with Comparator Module

      396
• 25.0 Comparator Voltage Reference Module

  397
  • 25.1 Configuring the Comparator Voltage Reference

    397
    • EQUATION 25-1:

      397
    • Register 25-1: CVRCON: Comparator Voltage Reference Control Register

      397
    • FIGURE 25-1: Comparator Voltage Reference Block Diagram

      398
  • 25.2 Voltage Reference Accuracy/Error

    398
  • 25.3 Operation During Sleep

    398
  • 25.4 Effects of a Reset

    398
  • 25.5 Connection Considerations

    398
    • FIGURE 25-2: Comparator Voltage Reference Output Buffer Example

      399
    • TABLE 25-1: Registers Associated with Comparator Voltage Reference

      399
• 26.0 High/Low-Voltage Detect (HLVD)

  401
  • Register 26-1: HLVDCON: High/Low-Voltage Detect Control Register

    401
  • 26.1 Operation

    402
    • FIGURE 26-1: HLVD Module Block Diagram (with External Input)

      402
  • 26.2 HLVD Setup

    403
  • 26.3 Current Consumption

    403
  • 26.4 HLVD Start-up Time

    403
    • FIGURE 26-2: Low-Voltage Detect Operation (VDIRMAG = 0)

      403
    • FIGURE 26-3: High-Voltage Detect Operation (VDIRMAG = 1)

      404
  • 26.5 Applications

    404
    • FIGURE 26-4: Typical Low-Voltage Detect Application

      404
  • 26.6 Operation During Sleep

    405
  • 26.7 Effects of a Reset

    405
    • TABLE 26-1: Registers Associated with High/Low-Voltage Detect Module

      405
• 27.0 Charge Time Measurement Unit (CTMU)

  407
  • FIGURE 27-1: CTMU Block Diagram

    407
  • 27.1 CTMU Registers

    408
    • Register 27-1: CTMUCONH: CTMU Control High Register

      408
    • Register 27-2: CTMUCONL: CTMU Control Low Register

      409
    • Register 27-3: CTMUICON: CTMU current Control Register

      410
  • 27.2 CTMU Operation

    411
    • 27.2.1 Theory of Operation

      411
    • 27.2.2 Current Source

      411
    • 27.2.3 Edge Selection and Control

      411
    • 27.2.4 Edge Status

      411
    • 27.2.5 Interrupts

      412
  • 27.3 CTMU Module Initialization

    412
  • 27.4 Calibrating the CTMU Module

    412
    • 27.4.1 Current Source Calibration

      412
      • FIGURE 27-2: CTMU Current Source Calibration Circuit

        413
      • EXAMPLE 27-1: Setup for CTMU Calibration Routines

        414
      • EXAMPLE 27-2: Current Calibration Routine

        415
    • 27.4.2 Capacitance Calibration

      416
      • EXAMPLE 27-3: Capacitance Calibration Routine

        417
  • 27.5 Measuring Capacitance with the CTMU

    418
    • 27.5.1 Absolute Capacitance Measurement

      418
    • 27.5.2 Relative Charge Measurement

      418
      • EXAMPLE 27-4: Routine for Capacitive Touch Switch

        419
  • 27.6 Measuring Time with the CTMU Module

    420
    • FIGURE 27-3: Typical Connections and Internal Configuration for Time Measurement

      420
  • 27.7 Creating a Delay with the CTMU Module

    421
    • FIGURE 27-4: Typical Connections and Internal Configuration for Pulse Delay Generation

      421
  • 27.8 Measuring Temperature Using the CTMU Module

    422
    • EXAMPLE 27-5: Routine for Temperature Measurement Using Internal Diode

      422
  • 27.9 Operation During Sleep/Idle Modes

    423
    • 27.9.1 Sleep Mode

      423
    • 27.9.2 Idle Mode

      423
  • 27.10 Effects of a Reset on CTMU

    423
    • TABLE 27-1: Registers Associated with CTMU Module

      423
• 28.0 Special Features of the CPU

  425
  • 28.1 Configuration Bits

    425
    • TABLE 28-1: Configuration Bits and Device IDs

      426
    • Register 28-1: CONFIG1L: Configuration Register 1 lOW (Byte Address 300000h)

      427
    • Register 28-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)

      428
    • Register 28-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)

      429
    • Register 28-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)

      430
    • Register 28-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)

      431
    • Register 28-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)

      431
    • Register 28-7: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)

      432
    • Register 28-8: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)(2)

      433
    • Register 28-9: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)(1)

      434
    • Register 28-10: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)(2)

      435
    • Register 28-11: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)(2)

      436
    • Register 28-12: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)(3)

      437
    • Register 28-13: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)(1)

      438
    • Register 28-14: DEVID1: Device ID Register 1 for the PIC18F87K90 Family

      439
    • Register 28-15: DEVID2: Device ID Register 2 for the PIC18F87K90 Family

      439
  • 28.2 Watchdog Timer (WDT)

    440
    • FIGURE 28-1: WDT Block Diagram

      440
    • 28.2.1 Control Register

      441
      • Register 28-16: WDTCON: Watchdog Timer Control Register

        441
      • TABLE 28-2: Summary of Watchdog Timer Registers

        441
  • 28.3 On-Chip Voltage Regulator

    442
    • 28.3.1 Regulator Enable/disable by Hardware

      442
      • FIGURE 28-2: Connections for the On-chip Regulator

        442
    • 28.3.2 Operation of regulator in Sleep

      443
      • TABLE 28-3: Sleep Mode Regulator Settings(1)

        443
  • 28.4 Two-Speed Start-up

    444
    • 28.4.1 Special Considerations for Using Two-Speed Start-up

      444
      • FIGURE 28-3: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)

        444
  • 28.5 Fail-Safe Clock Monitor

    445
    • FIGURE 28-4: FSCM Block Diagram

      445
    • 28.5.1 FSCM and the Watchdog Timer

      445
    • 28.5.2 Exiting Fail-Safe Operation

      445
      • FIGURE 28-5: FSCM Timing Diagram

        446
    • 28.5.3 FSCM Interrupts in Power-Managed Modes

      446
    • 28.5.4 POR or Wake From Sleep

      446
  • 28.6 Program Verification and Code Protection

    447
    • FIGURE 28-6: Code-Protected Program Memory for the PIC18F87K90 Family(1)

      447
    • TABLE 28-4: Summary of Code Protection Registers

      448
    • 28.6.1 Program Memory Code Protection

      448
      • FIGURE 28-7: Table Write (WRTn) Disallowed

        448
      • FIGURE 28-8: External Block Table Read (EBTRn) Disallowed

        449
      • FIGURE 28-9: External Block Table Read (EBTRn) Allowed

        449
    • 28.6.2 Data EEPROM Code Protection

      450
    • 28.6.3 Configuration Register Protection

      450
  • 28.7 ID Locations

    450
  • 28.8 In-Circuit Serial Programming

    450
  • 28.9 In-Circuit Debugger

    450
    • TABLE 28-5: Debugger Resources

      450
• 29.0 Instruction Set Summary

  451
  • 29.1 Standard Instruction Set

    451
    • TABLE 29-1: Opcode Field Descriptions

      452
    • FIGURE 29-1: General Format for Instructions

      453
    • TABLE 29-2: PIC18F87K90 Family Instruction Set

      454
    • 29.1.1 Standard Instruction Set

      457
  • 29.2 Extended Instruction Set

    493
    • 29.2.1 Extended Instruction Syntax

      493
      • TABLE 29-3: Extensions to the PIC18 Instruction Set

        493
    • 29.2.2 Extended Instruction Set

      494
    • 29.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode

      498
    • 29.2.4 Considerations When Enabling the Extended Instruction Set

      498
    • 29.2.5 Special Considerations with Microchip MPLAB® IDE Tools

      500
  • 30.0 Development Support

    501
• 31.0 Electrical Characteristics

  505
  • Absolute Maximum Ratings(†)

    505
    • FIGURE 31-1: Voltage-frequency Graph, Regulator Enabled (Industrial/Extended)(1)

      506
    • FIGURE 31-2: Voltage-frequency Graph, Regulator Disabled (Industrial/Extended)(1,2)

      506
  • 31.1 DC Characteristics: Supply Voltage PIC18F87K90 Family (Industrial/Extended)

    507
  • 31.2 DC Characteristics: Power-Down and Supply Current PIC18F87K90 Family (Industrial/Extended)

    508
  • 31.3 DC Characteristics: PIC18F87K90 Family (Industrial/Extended)

    519
  • 31.4 DC Characteristics: CTMU Current Source Specifications

    520
    • TABLE 31-1: Memory Programming Requirements

      521
    • TABLE 31-2: Comparator Specifications

      522
    • TABLE 31-3: Voltage Reference Specifications

      522
    • TABLE 31-4: Internal Voltage Regulator Specifications

      522
  • 31.5 AC (Timing) Characteristics

    523
    • 31.5.1 Timing Parameter Symbology

      523
    • 31.5.2 Timing Conditions

      524
      • TABLE 31-5: Temperature and Voltage Specifications – AC

        524
      • FIGURE 31-3: Load Conditions for Device Timing Specifications

        524
    • 31.5.3 Timing Diagrams and Specifications

      525
      • FIGURE 31-4: External Clock Timing

        525
      • TABLE 31-6: External Clock Timing Requirements

        525
      • TABLE 31-7: PLL Clock Timing Specifications (Vdd = 1.8V to 5.5V)

        526
      • TABLE 31-8: Internal RC Accuracy (INTOSC)

        526
      • FIGURE 31-5: CLKO and I/O Timing

        527
      • TABLE 31-9: CLKO and I/O Timing Requirements

        527
      • FIGURE 31-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

        528
      • FIGURE 31-7: Brown-out Reset Timing

        528
      • TABLE 31-10: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements

        529
      • FIGURE 31-8: High/Low-Voltage Detect Characteristics

        530
      • TABLE 31-11: High/Low-Voltage Detect Characteristics

        530
      • FIGURE 31-9: Timer0 and Timer1 External Clock Timings

        531
      • TABLE 31-12: Timer0 and Timer1 External Clock Requirements

        531
      • FIGURE 31-10: Capture/Compare/PWM Timings (ECCP1, ECCP2 Modules)

        532
      • TABLE 31-13: Capture/Compare/PWM Requirements (ECCP1, ECCP2 Modules)

        532
      • FIGURE 31-11: Example SPI Master Mode Timing (CKE = 0)

        533
      • TABLE 31-14: Example SPI Mode Requirements (Master Mode, Cke = 0)

        533
      • FIGURE 31-12: Example SPI Master Mode Timing (CKE = 1)

        534
      • TABLE 31-15: Example SPI Mode Requirements (Master Mode, CKE = 1)

        534
      • FIGURE 31-13: Example SPI Slave Mode Timing (CKE = 0)

        535
      • TABLE 31-16: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)

        535
      • FIGURE 31-14: Example SPI Slave Mode Timing (CKE = 1)

        536
      • TABLE 31-17: Example SPI Slave Mode Requirements (CKE = 1)

        536
      • FIGURE 31-15: I2C™ Bus Start/Stop Bits Timing

        537
      • TABLE 31-18: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)

        537
      • FIGURE 31-16: I2C™ Bus Data Timing

        538
      • TABLE 31-19: I2C™ Bus Data Requirements (Slave Mode)

        538
      • FIGURE 31-17: MSSP I2C™ Bus Start/Stop Bits Timing Waveforms

        539
      • TABLE 31-20: MSSP I2C™ Bus Start/Stop Bits Requirements

        539
      • FIGURE 31-18: MSSP I2C™ Bus Data Timing

        539
      • TABLE 31-21: MSSP I2C™ Bus Data Requirements

        540
      • FIGURE 31-19: EUSART Synchronous Transmission (Master/Slave) Timing

        541
      • TABLE 31-22: EUSART/AUSART Synchronous Transmission Requirements

        541
      • FIGURE 31-20: EUSART/AUSART Synchronous Receive (Master/Slave) Timing

        541
      • TABLE 31-23: EUSART/AUSART Synchronous Receive Requirements

        541
      • TABLE 31-24: Ultra Low-Power Wake-up Specifications

        541
      • TABLE 31-25: A/D Converter Characteristics: PIC18F87K90 Family (Industrial/Extended)

        542
      • FIGURE 31-21: A/D Conversion Timing

        543
      • TABLE 31-26: A/D Conversion Requirements

        543
• 32.0 Packaging Information

  545
  • 32.1 Package Marking Information

    545
  • 32.2 Package Details

    546
• Appendix A: Revision History

  553
  • Revision A (September 2009)

    553
  • Revision B (April 2010)

    553
  • Revision C (March 2011)

    553
  • Revision D (July 2011)

    553
• Appendix B: Migration From PIC18F85J90 and PIC18F87J90 to PIC18F87K90

  553
  • TABLE B-1: Notable Differences Between PIC18F87K90, PIC18F87J90 and PIC18F85J90 Families

    554
• INDEX

  555
• The Microchip Web Site

  567
• Customer Change Notification Service

  567
• Customer Support

  567
• Reader Response

  568
• Product Identification System

  569
• Worldwide Sales and Service

  570