Microchip Technology DM164134 マニュアル

目次

• High-Performance RISC CPU:

  3
• Peripheral Features:

  3
• Advanced Analog Features:

  3
• CAN bus Module Features:

  3
• Special Microcontroller Features:

  3
• Flash Technology:

  3
• Pin Diagrams

  4
• Table of Contents

  6
• Most Current Data Sheet

  7
• Errata

  7
• Customer Notification System

  7
• 1.0 Device Overview

  9
  • TABLE 1-1: PIC18FXX8 Device Features

    9
  • FIGURE 1-1: PIC18F248/258 Block Diagram

    10
  • FIGURE 1-2: PIC18F448/458 Block Diagram

    11
  • TABLE 1-2: PIC18FXX8 Pinout I/O Descriptions

    12
• 2.0 Oscillator Configurations

  19
  • 2.1 Oscillator Types

    19
  • 2.2 Crystal Oscillator/Ceramic Resonators

    19
    • FIGURE 2-1: Crystal/Ceramic Resonator Operation (HS, XT or LP Osc Configuration)

      19
    • TABLE 2-1: Ceramic Resonators

      19
    • TABLE 2-2: Capacitor Selection for Crystal Oscillator

      20
  • 2.3 RC Oscillator

    20
    • FIGURE 2-2: RC Oscillator Mode

      20
  • 2.4 External Clock Input

    21
    • FIGURE 2-3: External Clock Input Operation (EC Osc Configuration)

      21
    • FIGURE 2-4: External Clock Input Operation (ECIO Configuration)

      21
  • 2.5 HS4 (PLL)

    21
    • FIGURE 2-5: PLL Block Diagram

      21
  • 2.6 Oscillator Switching Feature

    22
    • 2.6.1 System Clock Switch Bit

      22
      • FIGURE 2-6: Device Clock Sources

        22
      • Register 2-1: OSCCON: Oscillator Control Register

        22
    • 2.6.2 Oscillator Transitions

      23
      • FIGURE 2-7: Timing Diagram for Transition From OSC1 to Timer1 Oscillator

        23
      • FIGURE 2-8: Timing Diagram for Transition Between Timer1 and OSC1 (HS, XT, LP)

        23
      • FIGURE 2-9: Timing for Transition Between Timer1 and OSC1 (HS with PLL)

        24
      • FIGURE 2-10: Timing for Transition Between Timer1 and OSC1 (RC, EC)

        24
  • 2.7 Effects of Sleep Mode on the OnChip Oscillator

    25
  • 2.8 Power-up Delays

    25
    • TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode

      25
• 3.0 Reset

  27
  • FIGURE 3-1: Simplified Block Diagram of On-Chip Reset Circuit

    27
  • 3.1 Power-on Reset (POR)

    28
  • 3.2 MCLR

    28
    • FIGURE 3-2: External Power-on Reset Circuit (for Slow Vdd Power-up)

      28
  • 3.3 Power-up Timer (PWRT)

    28
  • 3.4 Oscillator Start-up Timer (OST)

    28
  • 3.5 PLL Lock Time-out

    28
  • 3.6 Brown-out Reset (BOR)

    28
  • 3.7 Time-out Sequence

    29
    • TABLE 3-1: Time-out in Various Situations

      29
    • Register 3-1: RCON Register Bits and Positions

      29
    • TABLE 3-2: Status Bits, Their Significance and the Initialization Condition for RCON Register

      29
    • FIGURE 3-3: Time-out Sequence on Power-up (MCLR Tied to Vdd)

      30
    • FIGURE 3-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1

      30
    • FIGURE 3-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2

      30
    • FIGURE 3-6: Slow Rise Time (MCLR Tied to Vdd)

      31
    • FIGURE 3-7: Time-out Sequence on POR w/PLL Enabled (MCLR Tied to Vdd)

      31
    • TABLE 3-3: Initialization Conditions for All Registers

      32
• 4.0 Memory Organization

  39
  • 4.1 Program Memory Organization

    39
    • FIGURE 4-1: Program Memory Map and Stack for PIC18F248/448

      39
    • 4.1.1 Internal Program Memory Operation

      39
      • FIGURE 4-2: Program Memory Map and Stack for PIC18F258/458

        39
  • 4.2 Return Address Stack

    40
    • 4.2.1 Top-of-Stack Access

      40
    • 4.2.2 Return Stack Pointer (STKPTR)

      40
      • Register 4-1: STKPTR: Stack Pointer Register

        41
      • FIGURE 4-3: Return Address Stack and Associated Registers

        41
    • 4.2.3 PUSH and POP Instructions

      42
    • 4.2.4 Stack Full/Underflow Resets

      42
  • 4.3 Fast Register Stack

    42
    • EXAMPLE 4-1: Fast Register Stack Code Example

      42
  • 4.4 PCL, PCLATH and PCLATU

    42
  • 4.5 Clocking Scheme/Instruction Cycle

    43
    • FIGURE 4-4: Clock/Instruction Cycle

      43
  • 4.6 Instruction Flow/Pipelining

    43
  • 4.7 Instructions in Program Memory

    43
    • EXAMPLE 4-2: Instruction Pipeline Flow

      44
    • EXAMPLE 4-3: Instructions in Program Memory

      44
    • 4.7.1 Two-Word Instructions

      45
  • 4.8 Look-up Tables

    45
    • 4.8.1 Computed GOTO

      45
    • 4.8.2 Table Reads/Table Writes

      45
      • EXAMPLE 4-4: Two-Word Instructions

        45
  • 4.9 Data Memory Organization

    46
    • 4.9.1 General Purpose Register File

      46
    • 4.9.2 Special Function Registers

      46
      • FIGURE 4-5: Data Memory Map for PIC18F248/448

        47
      • FIGURE 4-6: Data Memory Map for PIC18F258/458

        48
      • TABLE 4-1: Special Function Register Map

        49
      • TABLE 4-2: Register File Summary

        51
  • 4.10 Access Bank

    56
  • 4.11 Bank Select Register (BSR)

    56
    • FIGURE 4-7: Direct Addressing

      56
  • 4.12 Indirect Addressing, INDF and FSR Registers

    57
    • EXAMPLE 4-5: How to Clear RAM (Bank 1) Using Indirect Addressing

      57
    • 4.12.1 Indirect Addressing Operation

      57
      • FIGURE 4-8: Indirect Addressing

        58
  • 4.13 Status Register

    59
    • Register 4-2: Status Register

      59
  • 4.14 RCON Register

    60
    • Register 4-3: RCON: Reset Control Register

      60
• 5.0 Data EEPROM Memory

  61
  • 5.1 EEADR Register

    61
  • 5.2 EECON1 and EECON2 Registers

    61
    • Register 5-1: EECON1: EEPROM Control Register 1

      62
  • 5.3 Reading the Data EEPROM Memory

    63
    • EXAMPLE 5-1: Data EEPROM Read

      63
  • 5.4 Writing to the Data EEPROM Memory

    63
    • EXAMPLE 5-2: Data EEPROM Write

      63
  • 5.5 Write Verify

    64
  • 5.6 Protection Against Spurious Write

    64
  • 5.7 Operation During Code-Protect

    64
  • 5.8 Using the Data EEPROM

    64
    • EXAMPLE 5-3: Data EEPROM Refresh Routine

      64
    • TABLE 5-1: Registers Associated with Data EEPROM Memory

      65
• 6.0 Flash Program Memory

  67
  • 6.1 Table Reads and Table Writes

    67
    • FIGURE 6-1: Table Read Operation

      67
    • FIGURE 6-2: Table Write Operation

      68
  • 6.2 Control Registers

    68
    • 6.2.1 EECON1 and EECON2 Registers

      68
      • Register 6-1: EECON1: EEPROM Control Register 1

        69
    • 6.2.2 TABLAT – Table Latch Register

      70
    • 6.2.3 TBLPTR – Table Pointer Register

      70
    • 6.2.4 Table Pointer Boundaries

      70
      • TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions

        70
      • FIGURE 6-3: Table Pointer Boundaries Based on Operation

        70
  • 6.3 Reading the Flash Program Memory

    71
    • FIGURE 6-4: Reads From Flash Program Memory

      71
    • EXAMPLE 6-1: Reading a Flash Program Memory Word

      71
  • 6.4 Erasing Flash Program Memory

    72
    • 6.4.1 Flash Program Memory Erase Sequence

      72
      • EXAMPLE 6-2: Erasing a Flash Program Memory Row

        72
  • 6.5 Writing to Flash Program Memory

    73
    • 6.5.1 Flash Program Memory Write Sequence

      73
      • FIGURE 6-5: Table Writes to Flash Program Memory

        73
      • EXAMPLE 6-3: Writing to Flash Program Memory

        74
      • EXAMPLE 6-3: Writing to Flash Program Memory (CONTINUED)

        75
    • 6.5.2 Write Verify

      75
    • 6.5.3 Unexpected Termination of Write Operation

      75
    • 6.5.4 Protection Against Spurious Writes

      75
  • 6.6 Flash Program Operation During Code Protection

    75
    • TABLE 6-2: Registers Associated with Program Flash Memory

      76
• 7.0 8 x 8 Hardware Multiplier

  77
  • 7.1 Introduction

    77
  • 7.2 Operation

    77
    • EXAMPLE 7-1: 8 x 8 Unsigned Multiply Routine

      77
    • EXAMPLE 7-2: 8 x 8 Signed Multiply Routine

      77
    • TABLE 7-1: Performance Comparison

      77
    • EQUATION 7-1: 16 x 16 Unsigned Multiplication Algorithm

      78
    • EXAMPLE 7-3: 16 x 16 Unsigned Multiply Routine

      78
    • EQUATION 7-2: 16 x 16 Signed Multiplication Algorithm

      78
    • EXAMPLE 7-4: 16 x 16 Signed Multiply Routine

      78
• 8.0 Interrupts

  79
  • FIGURE 8-1: Interrupt Logic

    80
  • 8.1 INTCON Registers

    81
    • Register 8-1: INTCON: Interrupt Control Register

      81
    • Register 8-2: INTCON2: Interrupt Control Register 2

      82
    • Register 8-3: INTCON3: Interrupt Control Register 3

      83
  • 8.2 PIR Registers

    84
    • Register 8-4: PIR1: Peripheral Interrupt Request (Flag) Register 1

      84
    • Register 8-5: PIR2: Peripheral Interrupt Request (Flag) Register 2

      85
    • Register 8-6: PIR3: Peripheral Interrupt Request (Flag) Register 3

      86
  • 8.3 PIE Registers

    87
    • Register 8-7: PIE1: Peripheral Interrupt Enable Register 1

      87
    • Register 8-8: PIE2: Peripheral Interrupt Enable Register 2

      88
    • Register 8-9: PIE3: Peripheral Interrupt Enable Register 3

      89
  • 8.4 IPR Registers

    90
    • Register 8-10: IPR1: Peripheral Interrupt Priority Register 1

      90
    • Register 8-11: IPR2: Peripheral Interrupt Priority Register 2

      91
    • Register 8-12: IPR3: Peripheral Interrupt Priority Register 3

      92
  • 8.5 RCON Register

    93
    • Register 8-13: RCON: Reset Control Register

      93
  • 8.6 INT Interrupts

    94
  • 8.7 TMR0 Interrupt

    94
  • 8.8 PORTB Interrupt-on-Change

    94
  • 8.9 Context Saving During Interrupts

    94
    • EXAMPLE 8-1: Saving Status, WREG and BSR Registers in RAM

      94
• 9.0 I/O Ports

  95
  • 9.1 PORTA, TRISA and LATA Registers

    95
    • EXAMPLE 9-1: Initializing PORTA

      95
    • FIGURE 9-1: RA3:RA0 and RA5 Pins Block Diagram

      96
    • FIGURE 9-2: RA4/T0CKI Pin Block Diagram

      96
    • FIGURE 9-3: OSC2/CLKO/RA6 Pin Block Diagram

      96
    • TABLE 9-1: PORTA Functions

      97
    • TABLE 9-2: Summary of Registers Associated with PORTA

      97
  • 9.2 PORTB, TRISB and LATB Registers

    98
    • EXAMPLE 9-2: Initializing PORTB

      98
    • FIGURE 9-4: RB7:RB4 Pins Block Diagram

      99
    • FIGURE 9-5: RB1:RB0 Pins Block Diagram

      99
    • FIGURE 9-6: RB2/CANTX/INT2 Pin Block Diagram

      100
    • FIGURE 9-7: RB3/CANRX Pin Block Diagram

      100
    • TABLE 9-3: PORTB Functions

      101
    • TABLE 9-4: Summary of Registers Associated with PORTB

      101
  • 9.3 PORTC, TRISC and LATC Registers

    102
    • EXAMPLE 9-3: Initializing PORTC

      102
    • FIGURE 9-8: PORTC Block Diagram (Peripheral Output Override)

      102
    • TABLE 9-5: PORTC Functions

      103
    • TABLE 9-6: Summary of Registers Associated with PORTC

      103
  • 9.4 PORTD, TRISD and LATD Registers

    104
    • EXAMPLE 9-4: Initializing PORTD

      104
    • FIGURE 9-9: PORTD Block Diagram in I/O Port Mode

      104
    • TABLE 9-7: PORTD Functions

      105
    • TABLE 9-8: Summary of Registers Associated with PORTD

      105
  • 9.5 PORTE, TRISE and LATE Registers

    106
    • EXAMPLE 9-5: Initializing PORTE

      106
    • FIGURE 9-10: PortE Block Diagram

      106
    • Register 9-1: TRISE Register

      107
    • TABLE 9-9: PORTE Functions

      108
    • TABLE 9-10: Summary of Registers Associated with PORTE

      108
• 10.0 Parallel Slave Port

  109
  • FIGURE 10-1: PORTD and PORTE Block Diagram (Parallel Slave Port)

    109
  • FIGURE 10-2: Parallel Slave Port Write Waveforms

    109
  • FIGURE 10-3: Parallel Slave Port Read Waveforms

    110
  • TABLE 10-1: Registers Associated with Parallel Slave Port

    110
• 11.0 Timer0 Module

  111
  • Register 11-1: T0CON: Timer0 Control Register

    111
  • FIGURE 11-1: Timer0 Block Diagram in 8-bit Mode

    112
  • FIGURE 11-2: Timer0 Block Diagram in 16-bit Mode

    112
  • 11.1 Timer0 Operation

    113
  • 11.2 Prescaler

    113
    • 11.2.1 Switching Prescaler Assignment

      113
  • 11.3 Timer0 Interrupt

    113
  • 11.4 16-Bit Mode Timer Reads and Writes

    113
    • TABLE 11-1: Registers Associated with Timer0

      113
• 12.0 Timer1 Module

  115
  • Register 12-1: T1CON: Timer1 Control Register

    115
  • 12.1 Timer1 Operation

    116
    • FIGURE 12-1: Timer1 Block Diagram

      116
    • FIGURE 12-2: Timer1 Block Diagram: 16-bit Read/Write Mode

      116
  • 12.2 Timer1 Oscillator

    117
    • TABLE 12-1: Capacitor Selection for the Alternate Oscillator

      117
  • 12.3 Timer1 Interrupt

    117
  • 12.4 Resetting Timer1 Using a CCP Trigger Output

    117
  • 12.5 Timer1 16-Bit Read/Write Mode

    117
    • TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter

      118
• 13.0 Timer2 Module

  119
  • 13.1 Timer2 Operation

    119
    • Register 13-1: T2CON: Timer2 Control Register

      119
  • 13.2 Timer2 Interrupt

    120
  • 13.3 Output of TMR2

    120
    • FIGURE 13-1: Timer2 Block Diagram

      120
    • TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter

      120
• 14.0 Timer3 Module

  121
  • Register 14-1: T3CON:Timer3 Control Register

    121
  • 14.1 Timer3 Operation

    122
    • FIGURE 14-1: Timer3 Block Diagram

      122
    • FIGURE 14-2: Timer3 Block Diagram Configured in 16-bit Read/Write Mode

      122
  • 14.2 Timer1 Oscillator

    123
  • 14.3 Timer3 Interrupt

    123
  • 14.4 Resetting Timer3 Using a CCP Trigger Output

    123
    • TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter

      123
• 15.0 Capture/Compare/PWM (CCP) Modules

  125
  • Register 15-1: CCP1CON: CCP1 Control Register

    125
  • 15.1 CCP1 Module

    126
    • TABLE 15-1: CCP1 Mode – Timer Resource

      126
  • 15.2 Capture Mode

    126
    • 15.2.1 CCP Pin Configuration

      126
    • 15.2.2 Timer1/Timer3 Mode Selection

      126
      • TABLE 15-2: Interaction of CCP1 and ECCP1 Modules

        126
    • 15.2.3 Software Interrupt

      127
    • 15.2.4 CCP1 Prescaler

      127
    • 15.2.5 CAN Message Time-Stamp

      127
      • EXAMPLE 15-1: Changing Between Capture Prescalers

        127
      • FIGURE 15-1: Capture Mode Operation Block Diagram

        127
  • 15.3 Compare Mode

    128
    • 15.3.1 CCP1 Pin Configuration

      128
    • 15.3.2 Timer1/Timer3 Mode Selection

      128
    • 15.3.3 Software Interrupt Mode

      128
    • 15.3.4 Special Event Trigger

      128
      • FIGURE 15-2: Compare Mode Operation Block Diagram

        128
      • TABLE 15-3: Registers Associated with Capture, Compare, Timer1 and Timer3

        129
  • 15.4 PWM Mode

    130
    • FIGURE 15-3: Simplified PWM Block Diagram

      130
    • FIGURE 15-4: PWM Output

      130
    • 15.4.1 PWM Period

      130
      • EQUATION 15-1:

        130
    • 15.4.2 PWM Duty Cycle

      130
      • EQUATION 15-2:

        130
      • EQUATION 15-3:

        131
    • 15.4.3 Setup for PWM Operation

      131
      • TABLE 15-4: Example PWM Frequencies and Resolutions at 40 MHz

        131
      • TABLE 15-5: Registers Associated with PWM and Timer2

        131
• 16.0 Enhanced Capture/ Compare/PWM (ECCP) Module

  133
  • Register 16-1: ECCP1Con: ECCP1 Control Register

    133
  • 16.1 ECCP1 Module

    134
    • TABLE 16-1: ECCP1 Mode – Timer Resource

      134
    • TABLE 16-2: Interaction of CCP1 and ECCP1 Modules

      134
    • TABLE 16-3: Pin Assignments for Various ECCP Modes

      134
  • 16.2 Capture Mode

    135
    • 16.2.1 CAN Message TIME-STAMP

      135
  • 16.3 Compare Mode

    135
    • 16.3.1 Special Event Trigger

      135
      • TABLE 16-4: Registers Associated with Enhanced Capture, Compare, Timer1 and Timer3

        135
  • 16.4 Standard PWM Mode

    136
  • 16.5 Enhanced PWM Mode

    136
    • 16.5.1 PWM Output Configurations

      136
      • FIGURE 16-1: Simplified Block Diagram of the Enhanced PWM Module

        136
      • FIGURE 16-2: PWM Output Relationships

        137
    • 16.5.2 Half-Bridge Mode

      138
      • FIGURE 16-3: Half-Bridge PWM Output

        138
      • FIGURE 16-4: Examples of Half-Bridge Output Mode Applications

        138
    • 16.5.3 Full-Bridge Mode

      139
      • FIGURE 16-5: Full-Bridge PWM Output

        139
      • FIGURE 16-6: Example of Full-Bridge Application

        140
      • FIGURE 16-7: PWM Direction Change

        141
      • FIGURE 16-8: PWM Direction Change at Near 100% Duty Cycle

        141
    • 16.5.4 Programmable Dead-Band Delay

      142
    • 16.5.5 System Implementation

      142
    • 16.5.6 Start-up Considerations

      142
    • 16.5.7 Output Polarity Configuration

      142
      • Register 16-2: ECCP1DEL: PWM Delay Register

        142
    • 16.5.8 Setup for PWM Operation

      143
      • TABLE 16-5: Registers Associated with Enhanced PWM and Timer2

        143
  • 16.6 Enhanced CCP Auto-Shutdown

    144
    • Register 16-3: ECCPAS: Enhanced Capture/Compare/PWM Auto-Shutdown Control Register

      144
• 17.0 Master Synchronous Serial Port (MSSP) Module

  145
  • 17.1 Master SSP (MSSP) Module Overview

    145
  • 17.2 Control Registers

    145
  • 17.3 SPI Mode

    145
    • FIGURE 17-1: MSSP Block Diagram (SPI™Mode)

      145
    • 17.3.1 Registers

      146
      • Register 17-1: SSPSTAT: MSSP Status Register (SPI Mode)

        146
      • Register 17-2: SSPCON1: MSSP Control Register 1 (SPI Mode)

        147
    • 17.3.2 Operation

      148
      • EXAMPLE 17-1: Loading the SSPBUF (SSPSR) Register

        148
    • 17.3.3 Enabling SPI I/O

      149
    • 17.3.4 Typical Connection

      149
      • FIGURE 17-2: SPI™ Master/Slave Connection

        149
    • 17.3.5 Master Mode

      150
      • FIGURE 17-3: SPI™ Mode Waveform (Master Mode)

        150
    • 17.3.6 Slave Mode

      151
    • 17.3.7 Slave Select Synchronization

      151
      • FIGURE 17-4: Slave Synchronization Waveform

        151
      • FIGURE 17-5: SPI™ Mode Waveform (Slave Mode with CKE = 0)

        152
      • FIGURE 17-6: SPI™ Mode Waveform (Slave Mode with CKE = 1)

        152
    • 17.3.8 Sleep Operation

      153
    • 17.3.9 Effects of a Reset

      153
    • 17.3.10 Bus Mode Compatibility

      153
      • TABLE 17-1: SPI™ Bus Modes

        153
      • TABLE 17-2: Registers Associated with SPI™ Operation

        153
  • 17.4 I2C Mode

    154
    • FIGURE 17-7: MSSP Block Diagram (I2C™ Mode)

      154
    • 17.4.1 Registers

      154
      • Register 17-3: SSPSTAT: MSSP Status Register (I2C Mode)

        155
      • Register 17-4: SSPCON1: MSSP Control Register 1 (I2C Mode)

        156
      • Register 17-5: SSPCON2: MSSP Control Register 2 (I2C Mode)

        157
    • 17.4.2 Operation

      158
    • 17.4.3 Slave Mode

      158
      • FIGURE 17-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)

        160
      • FIGURE 17-9: I2C™ Slave Mode Timing (Transmission, 7-bit Address)

        161
      • FIGURE 17-10: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)

        162
      • FIGURE 17-11: I2C™ Slave Mode Timing (Transmission, 10-bit Address)

        163
    • 17.4.4 Clock Stretching

      164
      • FIGURE 17-12: Clock Synchronization Timing

        165
      • FIGURE 17-13: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)

        166
      • FIGURE 17-14: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)

        167
    • 17.4.5 General Call Address Support

      168
      • FIGURE 17-15: Slave Mode General Call Address Sequence (7 or 10-bit Address Mode)

        168
    • 17.4.6 Master Mode

      169
      • FIGURE 17-16: MSSP Block Diagram (I2C™ Master Mode)

        169
    • 17.4.7 Baud Rate Generator

      171
      • FIGURE 17-17: Baud Rate Generator Block Diagram

        171
      • TABLE 17-3: I2C™ Clock Rate w/BRG

        171
      • FIGURE 17-18: Baud Rate Generator Timing with Clock Arbitration

        172
    • 17.4.8 I2C Master Mode Start Condition Timing

      173
      • FIGURE 17-19: First Start Bit Timing

        173
    • 17.4.9 I2C Master Mode Repeated Start Condition Timing

      174
      • FIGURE 17-20: Repeated Start Condition Waveform

        174
    • 17.4.10 I2C Master Mode Transmission

      175
    • 17.4.11 I2C Master Mode Reception

      175
      • FIGURE 17-21: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Address)

        176
      • FIGURE 17-22: I2C™ Master Mode Waveform (Reception, 7-bit Address)

        177
    • 17.4.12 Acknowledge Sequence Timing

      178
    • 17.4.13 Stop Condition Timing

      178
      • FIGURE 17-23: Acknowledge Sequence Waveform

        178
      • FIGURE 17-24: Stop Condition Receive or Transmit Mode

        178
    • 17.4.14 Sleep Operation

      179
    • 17.4.15 Effect of a Reset

      179
    • 17.4.16 Multi-Master Mode

      179
    • 17.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration

      179
      • FIGURE 17-25: Bus Collision Timing for Transmit and Acknowledge

        179
      • FIGURE 17-26: Bus Collision During Start Condition (SDA Only)

        180
      • FIGURE 17-27: Bus Collision During Start Condition (SCL = 0)

        181
      • FIGURE 17-28: BRG Reset Due to SDA Arbitration During Start Condition

        181
      • FIGURE 17-29: Bus Collision During a Repeated Start Condition (Case 1)

        182
      • FIGURE 17-30: Bus Collision During a Repeated Start Condition (Case 2)

        182
      • FIGURE 17-31: Bus Collision During a Stop Condition (Case 1)

        183
      • FIGURE 17-32: Bus Collision During a Stop Condition (Case 2)

        183
• 18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)

  185
  • Register 18-1: TXSTA: Transmit Status and Control Register

    185
  • Register 18-2: RCSTA: Receive Status and Control Register

    186
  • 18.1 USART Baud Rate Generator (BRG)

    187
    • 18.1.1 Sampling

      187
      • EXAMPLE 18-1: Calculating Baud Rate Error

        187
      • TABLE 18-1: Baud Rate Formula

        187
      • TABLE 18-2: Registers Associated with Baud Rate Generator

        187
      • TABLE 18-3: Baud Rates for Synchronous Mode

        188
      • TABLE 18-4: Baud Rates for Asynchronous Mode (BRGH = 0)

        189
      • TABLE 18-5: Baud Rates for Asynchronous Mode (BRGH = 1)

        190
  • 18.2 USART Asynchronous Mode

    191
    • 18.2.1 USART Asynchronous Transmitter

      191
      • FIGURE 18-1: USART Transmit Block Diagram

        191
      • FIGURE 18-2: Asynchronous Transmission

        192
      • FIGURE 18-3: Asynchronous Transmission (Back to Back)

        192
      • TABLE 18-6: Registers Associated with Asynchronous Transmission

        192
    • 18.2.2 USART Asynchronous Receiver

      193
    • 18.2.3 Setting Up 9-bit Mode with Address Detect

      193
      • FIGURE 18-4: USART Receive Block Diagram

        193
      • FIGURE 18-5: Asynchronous Reception

        194
      • TABLE 18-7: Registers Associated with Asynchronous Reception

        194
  • 18.3 USART Synchronous Master Mode

    195
    • 18.3.1 USART Synchronous Master Transmission

      195
      • TABLE 18-8: Registers Associated with Synchronous Master Transmission

        195
      • FIGURE 18-6: Synchronous Transmission

        196
      • FIGURE 18-7: Synchronous Transmission (Through TXEN)

        196
    • 18.3.2 USART Synchronous Master Reception

      197
      • TABLE 18-9: Registers Associated with Synchronous Master Reception

        197
      • FIGURE 18-8: Synchronous Reception (Master Mode, SREN)

        197
  • 18.4 USART Synchronous Slave Mode

    198
    • 18.4.1 USART Synchronous Slave Transmit

      198
    • 18.4.2 USART Synchronous Slave Reception

      198
      • TABLE 18-10: Registers Associated with Synchronous Slave Transmission

        199
      • TABLE 18-11: Registers Associated with Synchronous Slave Reception

        199
• 19.0 CAN Module

  201
  • 19.1 Overview

    201
    • 19.1.1 Overview of the Module

      201
    • 19.1.2 Transmit/Receive Buffers

      201
      • FIGURE 19-1: CAN Buffers and Protocol Engine Block Diagram

        202
  • 19.2 CAN Module Registers

    203
    • 19.2.1 CAN Control and Status Registers

      203
      • Register 19-1: CANCON: CAN Control Register

        203
      • Register 19-2: CANSTAT: CAN Status Register

        204
      • EXAMPLE 19-1: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers

        205
      • EXAMPLE 19-1: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers (Cont...

        206
      • Register 19-3: COMSTAT: Communication Status Register

        207
    • 19.2.2 CAN Transmit Buffer Registers

      208
      • Register 19-4: TXBnCON: Transmit Buffer n Control Registers

        208
      • Register 19-5: TXBnSIDH: Transmit Buffer n Standard Identifier, High Byte Registers

        209
      • Register 19-6: TXBnSIDL: Transmit Buffer n Standard Identifier, Low Byte Registers

        209
      • Register 19-7: TXBnEIDH: Transmit Buffer n Extended Identifier, High Byte Registers

        209
      • Register 19-8: TXBnEIDL: Transmit Buffer n Extended Identifier, Low Byte Registers

        210
      • Register 19-9: TXBnDm: Transmit Buffer n Data Field Byte m Registers

        210
      • Register 19-10: TXBnDLC: Transmit Buffer N Data Length Code Registers

        211
      • Register 19-11: TXERRCNT: Transmit Error Count Register

        211
    • 19.2.3 CAN Receive Buffer Registers

      212
      • Register 19-12: RXB0CON: Receive Buffer 0 Control Register

        212
      • Register 19-13: RXB1CON: Receive Buffer 1 Control Register

        213
      • Register 19-14: RXBnSIDH: Receive Buffer N Standard Identifier, High Byte Registers

        214
      • Register 19-15: RXBnSIDL: Receive Buffer N Standard Identifier, Low Byte Registers

        214
      • Register 19-16: RXBnEIDH: Receive Buffer N Extended Identifier, High Byte Registers

        214
      • Register 19-17: RXBnEIDL: Receive Buffer N Extended Identifier, Low Byte Registers

        215
      • Register 19-18: RXBnDLC: Receive Buffer N Data Length Code Registers

        215
      • Register 19-19: RXBnDm: Receive Buffer N Data Field Byte M Registers

        216
      • Register 19-20: RXERRCNT: Receive Error Count Register

        216
      • Register 19-21: RXFnSIDH: Receive Acceptance Filter N Standard Identifier Filter, High Byte Regis...

        217
      • Register 19-22: RXFnSIDL: Receive Acceptance Filter N Standard Identifier Filter, Low Byte Registers

        217
      • Register 19-23: RXFnEIDH: Receive Acceptance Filter N Extended Identifier, High Byte Registers

        218
      • Register 19-24: RXFnEIDL: Receive Acceptance Filter N Extended Identifier, Low Byte Registers

        218
      • Register 19-25: RXMnSIDH: Receive Acceptance Mask N Standard Identifier Mask, High Byte Registers

        218
      • Register 19-26: RXMnSIDL: Receive Acceptance Mask N Standard Identifier Mask, Low Byte Registers

        219
      • Register 19-27: RXMnEIDH: Receive Acceptance Mask N Extended Identifier Mask, High Byte Registers

        219
      • Register 19-28: RXMnEIDL: Receive Acceptance Mask N Extended Identifier Mask, Low Byte Registers

        219
    • 19.2.4 CAN Baud Rate Registers

      220
      • Register 19-29: BRGCON1: Baud Rate Control Register 1

        220
      • Register 19-30: BRGCON2: Baud Rate Control Register 2

        221
      • Register 19-31: BRGCON3: Baud Rate Control Register 3

        222
    • 19.2.5 CAN Module I/O Control Register

      223
      • Register 19-32: CIOCON: CAN I/O Control Register

        223
    • 19.2.6 CAN Interrupt Registers

      224
      • Register 19-33: PIR3: Peripheral Interrupt Request (Flag) Register 3

        224
      • Register 19-34: PIE3: Peripheral Interrupt Enable Register 3

        225
      • Register 19-35: IPR3: Peripheral Interrupt Priority Register 3

        226
      • TABLE 19-1: CAN Controller Register Map

        227
  • 19.3 CAN Modes of Operation

    228
    • 19.3.1 Configuration Mode

      228
    • 19.3.2 Disable Mode

      228
    • 19.3.3 Normal Mode

      228
    • 19.3.4 Listen Only Mode

      228
    • 19.3.5 Loopback Mode

      229
    • 19.3.6 Error Recognition Mode

      229
  • 19.4 CAN Message Transmission

    229
    • 19.4.1 Transmit Buffers

      229
    • 19.4.2 Transmit Priority

      229
      • FIGURE 19-2: Transmit Buffer Block Diagram

        229
    • 19.4.3 Initiating Transmission

      230
    • 19.4.4 Aborting Transmission

      230
      • FIGURE 19-3: Internal Transmit Message Flowchart

        231
  • 19.5 Message Reception

    232
    • 19.5.1 Receive Message Buffering

      232
    • 19.5.2 Receive Buffers

      232
    • 19.5.3 Receive Priority

      232
    • 19.5.4 Time-Stamping

      232
      • FIGURE 19-4: Receive Buffer Block Diagram

        232
      • FIGURE 19-5: Internal Message Reception Flowchart

        233
  • 19.6 Message Acceptance Filters and Masks

    234
    • TABLE 19-2: Filter/Mask Truth Table

      234
    • FIGURE 19-6: Message Acceptance Mask and Filter Operation

      234
  • 19.7 Baud Rate Setting

    235
    • FIGURE 19-7: Bit Time Partitioning

      235
    • 19.7.1 Time Quanta

      236
      • EXAMPLE 19-2: Calculating Tq, Nominal Bit Rate and Nominal Bit Time

        236
    • 19.7.2 Synchronization Segment

      236
    • 19.7.3 Propagation Segment

      236
    • 19.7.4 Phase Buffer Segments

      236
    • 19.7.5 Sample Point

      236
    • 19.7.6 Information Processing Time

      236
  • 19.8 Synchronization

    237
    • 19.8.1 Hard Synchronization

      237
    • 19.8.2 Resynchronization

      237
    • 19.8.3 synchronization rules

      237
      • FIGURE 19-8: Lengthening a Bit Period (Adding SJW to Phase Segment 1)

        237
      • FIGURE 19-9: Shortening a Bit Period (Subtracting SJW From Phase Segment 2)

        238
  • 19.9 Programming Time Segments

    238
  • 19.10 Oscillator Tolerance

    238
  • 19.11 Bit Timing Configuration Registers

    238
    • 19.11.1 BRGCON1

      238
    • 19.11.2 BRGCON2

      238
    • 19.11.3 BRGCON3

      238
  • 19.12 Error Detection

    239
    • 19.12.1 CRC Error

      239
    • 19.12.2 Acknowledge Error

      239
    • 19.12.3 Form Error

      239
    • 19.12.4 Bit Error

      239
    • 19.12.5 Stuff Bit Error

      239
    • 19.12.6 Error States

      239
    • 19.12.7 Error Modes and Error Counters

      239
      • FIGURE 19-10: Error Modes State Diagram

        240
  • 19.13 CAN Interrupts

    240
    • 19.13.1 Interrupt Code Bits

      240
    • 19.13.2 Transmit Interrupt

      240
    • 19.13.3 Receive Interrupt

      240
      • TABLE 19-3: Values for ICODE<2:0>

        241
    • 19.13.4 Message Error Interrupt

      241
    • 19.13.5 Bus Activity Wake-up Interrupt

      241
    • 19.13.6 Error Interrupt

      241
    • 19.13.7 Interrupt Acknowledge

      241
• 20.0 Compatible 10-Bit Analog- to-Digital Converter (A/D) Module

  243
  • Register 20-1: ADCON0: A/D Control Register 0

    243
  • Register 20-2: ADCON1: A/D Control Register 1

    244
  • FIGURE 20-1: A/D Block Diagram

    245
  • 20.1 A/D Acquisition Requirements

    246
    • FIGURE 20-2: Analog Input Model

      246
    • EQUATION 20-1: Acquisition Time

      247
    • EQUATION 20-2: A/D Minimum Charging Time

      247
    • EXAMPLE 20-1: Calculating The Minimum Required Acquisition Time

      247
  • 20.2 Selecting the A/D Conversion Clock

    248
  • 20.3 Configuring Analog Port Pins

    248
    • TABLE 20-1: Tad vs. Device Operating Frequencies

      248
    • TABLE 20-2: Tad vs. Device Operating Frequencies (for Extended, LF Devices)

      248
  • 20.4 A/D Conversions

    249
    • 20.4.1 A/D Result Registers

      249
      • FIGURE 20-3: A/D Result Justification

        249
  • 20.5 Use of the ECCP Trigger

    250
    • FIGURE 20-4: A/D Conversion Tad Cycles

      250
    • TABLE 20-3: Summary of A/D Registers

      250
• 21.0 Comparator Module

  251
  • Register 21-1: CMCON: Comparator Control Register

    251
  • 21.1 Comparator Configuration

    252
    • FIGURE 21-1: Comparator I/O Operating Modes

      252
  • 21.2 Comparator Operation

    253
  • 21.3 Comparator Reference

    253
    • FIGURE 21-2: Single Comparator

      253
    • 21.3.1 External Reference Signal

      253
    • 21.3.2 Internal Reference Signal

      253
  • 21.4 Comparator Response Time

    253
  • 21.5 Comparator Outputs

    253
    • FIGURE 21-3: Comparator Output Block Diagram

      254
  • 21.6 Comparator Interrupts

    254
  • 21.7 Comparator Operation During Sleep

    255
  • 21.8 Effects of a Reset

    255
  • 21.9 Analog Input Connection Considerations

    255
    • FIGURE 21-4: Analog Input Model

      255
    • TABLE 21-1: Registers Associated with Comparator Module

      256
• 22.0 Comparator Voltage Reference Module

  257
  • 22.1 Configuring the Comparator Voltage Reference

    257
    • EQUATION 22-1:

      257
    • EQUATION 22-2:

      257
    • Register 22-1: CVRCON: Comparator Voltage Reference Control Register

      257
    • FIGURE 22-1: Voltage Reference Block Diagram

      258
  • 22.2 Voltage Reference Accuracy/Error

    258
  • 22.3 Operation During Sleep

    258
  • 22.4 Effects of a Reset

    258
  • 22.5 Connection Considerations

    258
    • FIGURE 22-2: Voltage Reference Output Buffer Example

      259
    • TABLE 22-1: Registers Associated with Comparator Voltage Reference

      259
• 23.0 Low-Voltage Detect

  261
  • FIGURE 23-1: Typical Low-Voltage Detect Application

    261
  • FIGURE 23-2: Low-Voltage Detect (LVD) Block Diagram

    262
  • FIGURE 23-3: Low-Voltage Detect (LVD) with External Input Block Diagram

    262
  • 23.1 Control Register

    263
    • Register 23-1: LVDCON: Low-Voltage Detect Control Register

      263
  • 23.2 Operation

    264
    • FIGURE 23-4: Low-Voltage Detect Waveforms

      264
    • 23.2.1 Reference Voltage Set Point

      265
    • 23.2.2 Current Consumption

      265
  • 23.3 Operation During Sleep

    265
  • 23.4 Effects of a Reset

    265
• 24.0 Special Features of the CPU

  267
  • 24.1 Configuration Bits

    267
    • TABLE 24-1: Configuration Bits and Device IDs

      267
    • Register 24-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)

      268
    • Register 24-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)

      268
    • Register 24-3: config2h: Configuration Register 2 High (Byte Address 300003h)

      269
    • Register 24-4: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)

      269
    • Register 24-5: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)

      270
    • Register 24-6: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)

      270
    • Register 24-7: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)

      271
    • Register 24-8: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)

      271
    • Register 24-9: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)

      272
    • Register 24-10: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)

      272
    • Register 24-11: DEVID1: Device ID Register 1 for PIC18FXX8 Devices (Byte Address 3FFFFEh)

      273
    • Register 24-12: DEVID2: Device ID Register 2 for PIC18FXX8 Devices (Byte Address 3FFFFFh)

      273
  • 24.2 Watchdog Timer (WDT)

    274
    • 24.2.1 Control Register

      274
      • Register 24-13: WDTCON: Watchdog Timer Control Register

        274
    • 24.2.2 WDT Postscaler

      275
      • FIGURE 24-1: Watchdog Timer Block Diagram

        275
      • TABLE 24-2: Summary of Watchdog Timer Registers

        275
  • 24.3 Power-Down Mode (Sleep)

    276
    • 24.3.1 Wake-up From Sleep

      276
    • 24.3.2 Wake-up Using Interrupts

      276
      • FIGURE 24-2: Wake-up From Sleep Through Interrupt(1,2)

        277
  • 24.4 Program Verification and Code Protection

    278
    • FIGURE 24-3: Code-Protected Program Memory for PIC18FXX8

      278
    • TABLE 24-3: Summary of Code Protection Registers

      278
    • 24.4.1 Program Memory Code Protection

      279
      • FIGURE 24-4: Table Write (WRTn) Disallowed

        279
      • FIGURE 24-5: External Block Table Read (EBTRn) Disallowed

        280
      • FIGURE 24-6: External Block Table Read (EBTRn) Allowed

        280
    • 24.4.2 Data EEPROM Code Protection

      281
    • 24.4.3 Configuration Register Protection

      281
  • 24.5 ID Locations

    281
  • 24.6 In-Circuit Serial Programming

    281
  • 24.7 In-Circuit Debugger

    281
  • 24.8 Low-Voltage ICSP Programming

    281
• 25.0 Instruction Set Summary

  283
  • 25.1 ReadModify-Write Operations

    283
    • TABLE 25-1: Opcode Field Descriptions

      284
    • FIGURE 25-1: General Format for Instructions

      285
    • TABLE 25-2: PIC18FXXX Instruction Set

      286
  • 25.2 Instruction Set

    289
• 26.0 Development Support

  325
  • 26.1 MPLAB Integrated Development Environment Software

    325
  • 26.2 MPASM Assembler

    325
  • 26.3 MPLAB C17 and MPLAB C18 C Compilers

    326
  • 26.4 MPLINK Object Linker/ MPLIB Object Librarian

    326
  • 26.5 MPLAB C30 C Compiler

    326
  • 26.6 MPLAB ASM30 Assembler, Linker and Librarian

    326
  • 26.7 MPLAB SIM Software Simulator

    326
  • 26.8 MPLAB SIM30 Software Simulator

    326
  • 26.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator

    327
  • 26.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator

    327
  • 26.11 MPLAB ICD 2 In-Circuit Debugger

    327
  • 26.12 PRO MATE II Universal Device Programmer

    327
  • 26.13 MPLAB PM3 Device Programmer

    327
  • 26.14 PICSTART Plus Development Programmer

    328
  • 26.15 PICDEM 1 PICmicro Demonstration Board

    328
  • 26.16 PICDEM.net Internet/Ethernet Demonstration Board

    328
  • 26.17 PICDEM 2 Plus Demonstration Board

    328
  • 26.18 PICDEM 3 PIC16C92X Demonstration Board

    328
  • 26.19 PICDEM 4 8/14/18-Pin Demonstration Board

    328
  • 26.20 PICDEM 17 Demonstration Board

    329
  • 26.21 PICDEM 18R PIC18C601/801 Demonstration Board

    329
  • 26.22 PICDEM LIN PIC16C43X Demonstration Board

    329
  • 26.23 PICkitTM 1 Flash Starter Kit

    329
  • 26.24 PICDEM USB PIC16C7X5 Demonstration Board

    329
  • 26.25 Evaluation and Programming Tools

    329
• 27.0 Electrical Characteristics

  331
  • Absolute Maximum Ratings(†)

    331
    • FIGURE 27-1: PIC18FXX8 Voltage-Frequency Graph (Industrial)

      332
    • FIGURE 27-2: PIC18FXX8 Voltage-Frequency Graph (Extended)

      332
    • FIGURE 27-3: PIC18LFXX8 Voltage-Frequency Graph (Industrial)

      333
  • 27.1 DC Characteristics

    334
  • 27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial)

    338
    • FIGURE 27-4: Low-Voltage Detect Characteristics

      340
    • TABLE 27-1: Low-Voltage Detect Characteristics

      340
    • TABLE 27-2: DC Characteristics: EEPROM and Enhanced Flash

      341
    • TABLE 27-3: Comparator Specifications

      342
    • TABLE 27-4: Voltage Reference Specifications

      342
  • 27.3 AC (Timing) Characteristics

    343
    • 27.3.1 Timing Parameter Symbology

      343
    • 27.3.2 Timing Conditions

      344
      • TABLE 27-5: Temperature and Voltage Specifications – AC

        344
      • FIGURE 27-5: Load Conditions for Device Timing Specifications

        344
    • 27.3.3 Timing Diagrams and Specifications

      345
      • FIGURE 27-6: External Clock Timing

        345
      • TABLE 27-6: External Clock Timing Requirements

        345
      • TABLE 27-7: PLL Clock Timing Specifications (Vdd = 4.2 to 5.5V)

        346
      • FIGURE 27-7: CLKO and I/O Timing

        346
      • TABLE 27-8: CLKO and I/O Timing Requirements

        346
      • FIGURE 27-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

        347
      • FIGURE 27-9: Brown-out Reset and Low-Voltage Detect Timing

        347
      • TABLE 27-9: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and...

        347
      • FIGURE 27-10: Timer0 and Timer1 External Clock Timings

        348
      • TABLE 27-10: Timer0 and Timer1 External Clock Requirements

        348
      • FIGURE 27-11: Capture/Compare/PWM Timings (CCP1 and ECCP1)

        349
      • TABLE 27-11: Capture/Compare/PWM Requirements (CCP1 and ECCP1)

        349
      • FIGURE 27-12: Parallel Slave Port Timing (PIC18F248 and PIC18F458)

        350
      • TABLE 27-12: Parallel Slave Port Requirements (PIC18F248 and PIC18F458)

        350
      • FIGURE 27-13: Example SPI™ Master Mode Timing (CKE=0)

        351
      • TABLE 27-13: Example SPI™ Mode Requirements (Master Mode, CKE=0)

        351
      • FIGURE 27-14: Example SPI™ Master Mode Timing (CKE=1)

        352
      • TABLE 27-14: Example SPI™ Mode Requirements (Master Mode, CKE=1)

        352
      • FIGURE 27-15: Example SPI™ Slave Mode Timing (CKE=0)

        353
      • TABLE 27-15: Example SPI™ Mode Requirements, Slave Mode Timing (CKE=0)

        353
      • FIGURE 27-16: Example SPI™ Slave Mode Timing (CKE=1)

        354
      • TABLE 27-16: Example SPI™ Slave Mode Requirements (CKE=1)

        354
      • FIGURE 27-17: I2C™ Bus Start/Stop Bits Timing

        355
      • TABLE 27-17: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)

        355
      • FIGURE 27-18: I2C™ Bus Data Timing

        355
      • TABLE 27-18: I2C™ Bus Data Requirements (Slave Mode)

        356
      • FIGURE 27-19: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms

        357
      • TABLE 27-19: Master SSP I2C™ Bus Start/Stop Bits Requirements

        357
      • FIGURE 27-20: Master SSP I2C™ Bus Data Timing

        357
      • TABLE 27-20: Master SSP I2C™ Bus Data Requirements

        358
      • FIGURE 27-21: USART Synchronous Transmission (Master/Slave) Timing

        359
      • TABLE 27-21: USART Synchronous Transmission Requirements

        359
      • FIGURE 27-22: USART Synchronous Receive (Master/Slave) Timing

        359
      • TABLE 27-22: USART Synchronous Receive Requirements

        359
      • TABLE 27-23: A/D Converter Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial)

        360
      • FIGURE 27-23: A/D Conversion Timing

        361
      • TABLE 27-24: A/D Conversion Requirements

        361
• 28.0 DC and AC Characteristics Graphs and Tables

  363
  • FIGURE 28-1: Typical Idd vs. Fosc Over Vdd (Hs Mode)

    363
  • FIGURE 28-2: Maximum Idd vs. Fosc Over Vdd (Hs Mode)

    363
  • FIGURE 28-3: Typical Idd vs. Fosc Over Vdd (HS/PLL Mode)

    364
  • FIGURE 28-4: Maximum Idd vs. Fosc Over Vdd (HS/PLL Mode)

    364
  • FIGURE 28-5: Typical Idd vs. Fosc Over Vdd (XT Mode)

    365
  • FIGURE 28-6: Maximum Idd vs. Fosc Over Vdd (XT Mode)

    365
  • FIGURE 28-7: Typical Idd vs. Fosc Over Vdd (LP Mode)

    366
  • FIGURE 28-8: Maximum Idd vs. Fosc Over Vdd (LP Mode)

    366
  • FIGURE 28-9: Typical Idd vs. Fosc Over Vdd (EC Mode)

    367
  • FIGURE 28-10: Maximum Idd vs. Fosc Over Vdd (EC Mode)

    367
  • FIGURE 28-11: Typical and Maximum Idd vs. Vdd (Timer1 as Main Oscillator 32.768kHz, C1 and C2 = ...

    368
  • FIGURE 28-12: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 20 pF, +25°C)

    368
  • FIGURE 28-13: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 100pF, +25°C)

    369
  • FIGURE 28-14: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 300pF, +25°C)

    369
  • FIGURE 28-15: Ipd vs. Vdd, -40°C to +125°C (Sleep Mode, All Peripherals Disabled)

    370
  • FIGURE 28-16: DIbor vs. Vdd Over Temperature (BOR Enabled, Vbor = 2.00-2.16V)

    370
  • FIGURE 28-17: Typical and Maximum DItmr1 vs. Vdd Over Temperature (-10°C to +70°C, Timer1 with Os...

    371
  • FIGURE 28-18: Typical and Maximum DIwdt vs. Vdd Over Temperature (WDT Enabled)

    371
  • FIGURE 28-19: Typical, Minimum and Maximum WDT Period vs. Vdd (-40°C to +125°C)

    372
  • FIGURE 28-20: DIlvd vs. Vdd Over Temperature (LVD Enabled, Vlvd = 4.5 - 4.78V)

    372
  • FIGURE 28-21: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 5V, -40°C to +125°C)

    373
  • FIGURE 28-22: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 3V, -40°C to +125°C)

    373
  • FIGURE 28-23: Typical and Maximum Vol vs. Iol (Vdd = 5V, -40°C to +125°C)

    374
  • FIGURE 28-24: Typical and Maximum Vol vs. Iol (Vdd = 3V, -40°C to +125°C)

    374
  • FIGURE 28-25: Minimum and Maximum Vin vs. Vdd (ST Input, -40°C to +125°C)

    375
  • FIGURE 28-26: Minimum and Maximum Vin vs. Vdd (TTL Input, -40°C to +125°C)

    375
  • FIGURE 28-27: Minimum and Maximum Vin vs. Vdd (I2C™ Input, -40°C to +125°C)

    376
  • FIGURE 28-28: A/D Nonlinearity vs. Vrefh (Vdd = Vrefh, -40°C to +125°C)

    376
  • FIGURE 28-29: A/D Nonlinearity vs. Vrefh (Vdd = 5V, -40°C to +125°C)

    377
• 29.0 Packaging Information

  379
  • 29.1 Package Marking Information

    379
  • 29.1 Package Marking Information (Continued)

    380
  • 29.2 Package Details

    381
  • 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)

    381
  • 28-Lead Plastic Small Outline (SO) –Wide, 300 mil Body (SOIC)

    382
  • 40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)

    383
  • 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)

    384
  • 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

    385
• Appendix A: Data Sheet Revision History

  387
  • Revision A (June 2001)

    387
  • Revision B (May 2002)

    387
  • Revision C (January 2003)

    387
  • Revision D (September 2004)

    387
  • Revision E (October 2006)

    387
• Appendix B: Device Differences

  387
  • TABLE B-1: Device Differences

    387
• Appendix C: Device Migrations

  388
• Appendix D: Migrating From Other PICmicro® Devices

  388
• INDEX

  389
• The Microchip Web Site

  399
• Customer Change Notification Service

  399
• Customer Support

  399
• Reader Response

  400
• PIC18FXX8 Product Identification System

  401
• Worldwide Sales and Service

  402