Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP マニュアル

目次

• Low-Power Features:

  3
• Special Microcontroller Features:

  3
• Peripheral Highlights:

  4
• Pin Diagrams – PIC18F6XK22

  5
• Pin Diagrams – PIC18F8XK22

  6
• Table of Contents

  7
• Most Current Data Sheet

  8
• Errata

  8
• Customer Notification System

  8
• 1.0 Device Overview

  9
  • 1.1 Core Features

    9
    • 1.1.1 nanoWatt Technology

      9
    • 1.1.2 Oscillator Options and Features

      9
    • 1.1.3 Memory Options

      9
    • 1.1.4 External Memory Bus

      9
    • 1.1.5 Extended Instruction Set

      9
    • 1.1.6 Easy Migration

      10
  • 1.2 Other Special Features

    10
  • 1.3 Details on Individual Family Members

    11
    • TABLE 1-1: Device Features for the PIC18F6XK22 (64-pin Devices)

      12
    • TABLE 1-2: Device Features for the PIC18F8XK22 (80-pin Devices)

      12
    • FIGURE 1-1: PIC18F6XK22 (64-pin) Block Diagram

      13
    • FIGURE 1-2: PIC18F8XK22 (80-pin) Block Diagram

      14
    • TABLE 1-3: PIC18F6XK22 Pinout I/O Descriptions

      15
    • TABLE 1-4: PIC18F8XK22 Pinout I/O Descriptions

      24
• 2.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers

  37
  • 2.1 Basic Connection Requirements

    37
    • FIGURE 2-1: Recommended Minimum connections

      37
  • 2.2 Power Supply Pins

    38
  • 2.3 Master Clear (MCLR) Pin

    38
    • FIGURE 2-2: Example of MCLR Pin Connections

      38
  • 2.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)

    39
    • FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap

      39
    • TABLE 2-1: Suitable Capacitor Equivalents

      39
    • FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics

      40
  • 2.5 ICSP Pins

    40
  • 2.6 External Oscillator Pins

    41
  • 2.7 Unused I/Os

    41
    • FIGURE 2-5: Suggested Placement of the Oscillator Circuit

      41
• 3.0 Oscillator Configurations

  43
  • 3.1 Oscillator Types

    43
    • TABLE 3-1: HS, EC, XT, LP and RC Modes: Ranges and Settings

      44
    • FIGURE 3-1: PIC18F87K22 Family Clock Diagram

      44
  • 3.2 Control Registers

    45
    • Register 3-1: OSCCON: Oscillator Control Register(1)

      45
    • Register 3-2: OSCCON2: Oscillator Control Register 2

      46
    • Register 3-3: OSCTUNE: Oscillator Tuning Register

      47
  • 3.3 Clock Sources and Oscillator Switching

    48
    • 3.3.1 OSC1/OSC2 Oscillator

      48
    • 3.3.2 Clock Source Selection

      48
    • 3.3.3 Oscillator Transitions

      49
  • 3.4 RC Oscillator

    49
    • FIGURE 3-2: RC Oscillator Mode

      49
    • FIGURE 3-3: RCIO Oscillator Mode

      49
  • 3.5 External Oscillator Modes

    50
    • 3.5.1 Crystal Oscillator/Ceramic Resonators (HS Modes)

      50
      • TABLE 3-2: Capacitor Selection for Ceramic Resonators

        50
      • TABLE 3-3: Capacitor Selection for Crystal Oscillator

        50
      • FIGURE 3-4: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)

        50
    • 3.5.2 External Clock Input (EC Modes)

      51
      • FIGURE 3-5: External Clock Input Operation (EC Configuration)

        51
      • FIGURE 3-6: External Clock Input Operation (HS OSC Configuration)

        51
    • 3.5.3 PLL Frequency Multiplier

      51
      • FIGURE 3-7: PLL Block Diagram

        51
  • 3.6 Internal Oscillator Block

    52
    • 3.6.1 INTIO Modes

      52
      • FIGURE 3-8: INTIO1 Oscillator Mode

        52
      • FIGURE 3-9: INTIO2 Oscillator Mode

        52
    • 3.6.2 INTPLL Modes

      52
    • 3.6.3 Internal Oscillator Output Frequency and Tuning

      53
    • 3.6.4 INTOSC Frequency Drift

      53
  • 3.7 Reference Clock Output

    53
    • Register 3-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER

      54
  • 3.8 Effects of Power-Managed Modes on the Various Clock Sources

    55
  • 3.9 Power-up Delays

    55
    • TABLE 3-4: OSC1 and OSC2 Pin States in Sleep Mode

      55
• 4.0 Power-Managed Modes

  57
  • 4.1 Selecting Power-Managed Modes

    57
    • 4.1.1 Clock Sources

      57
    • 4.1.2 Entering Power-Managed Modes

      57
      • TABLE 4-1: Power-Managed Modes

        57
    • 4.1.3 Clock Transitions and Status Indicators

      58
      • TABLE 4-2: System Clock Indicator

        58
    • 4.1.4 Multiple Sleep Commands

      58
  • 4.2 Run Modes

    58
    • 4.2.1 PRI_RUN Mode

      58
    • 4.2.2 SEC_RUN Mode

      58
      • FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode

        59
      • FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)

        59
    • 4.2.3 RC_RUN Mode

      60
      • TABLE 4-3: Internal Oscillator Frequency Stability Bits

        60
      • FIGURE 4-3: Transition Timing to RC_RUN Mode

        61
      • FIGURE 4-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode

        61
  • 4.3 Sleep Mode

    62
  • 4.4 Idle Modes

    62
    • FIGURE 4-5: Transition Timing for Entry to Sleep Mode

      62
    • FIGURE 4-6: Transition Timing for Wake From Sleep (HSPLL)

      62
    • 4.4.1 PRI_IDLE Mode

      63
    • 4.4.2 SEC_IDLE Mode

      63
      • FIGURE 4-7: Transition Timing for Entry to Idle Mode

        63
      • FIGURE 4-8: Transition Timing for Wake From Idle to Run Mode

        63
    • 4.4.3 RC_IDLE Mode

      64
  • 4.5 Selective Peripheral Module Control

    64
    • Register 4-1: PMD3: Peripheral Module Disable Register 3

      65
    • Register 4-2: PMD2: Peripheral Module Disable Register 2

      66
    • Register 4-3: PMD1: Peripheral Module Disable Register 1

      67
    • Register 4-4: PMD0: Peripheral Module Disable Register 0

      68
  • 4.6 Exiting Idle and Sleep Modes

    69
    • 4.6.1 Exit By Interrupt

      69
    • 4.6.2 Exit By WDT Time-out

      69
    • 4.6.3 Exit By Reset

      69
    • 4.6.4 Exit Without an Oscillator Start-up Delay

      69
  • 4.7 Ultra Low-Power Wake-up

    70
    • EXAMPLE 4-1: Ultra Low-Power Wake-up Initialization

      70
    • FIGURE 4-9: Ultra Low-Power Wake-up Initialization

      70
    • TABLE 4-4: Exit Delay on Wake-up By Reset From Sleep Mode or Any Idle Mode (By Clock Sources)

      71
• 5.0 Reset

  73
  • 5.1 RCON Register

    73
    • FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit

      73
    • Register 5-1: RCON: Reset Control Register

      74
  • 5.2 Master Clear (MCLR)

    75
  • 5.3 Power-on Reset (POR)

    75
  • 5.4 Brown-out Reset (BOR)

    75
    • FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)

      75
    • 5.4.1 Detecting BOR

      75
  • 5.5 Configuration Mismatch (CM)

    76
  • 5.6 Power-up Timer (PWRT)

    76
    • 5.6.1 Time-out Sequence

      76
      • FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)

        76
      • FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1

        77
      • FIGURE 5-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2

        77
      • FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)

        77
  • 5.7 Reset State of Registers

    78
    • TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register

      78
    • TABLE 5-2: Initialization Conditions for All Registers

      79
• 6.0 Memory Organization

  87
  • FIGURE 6-1: Memory Maps for PIC18F87K22 Family Devices

    87
  • 6.1 Program Memory Organization

    88
    • 6.1.1 Hard Memory Vectors

      88
      • FIGURE 6-2: Hard Vector for PIC18F87K22 Family Devices

        88
    • 6.1.2 Program Counter

      89
    • 6.1.3 Return Address Stack

      89
      • FIGURE 6-3: Return Address Stack and Associated Registers

        89
      • Register 6-1: STKPTR: Stack Pointer Register

        90
    • 6.1.4 Fast Register Stack

      91
      • EXAMPLE 6-1: Fast Register Stack Code Example

        91
    • 6.1.5 Look-up Tables in Program Memory

      91
      • EXAMPLE 6-2: Computed GOTO Using an Offset Value

        91
  • 6.2 PIC18 Instruction Cycle

    92
    • 6.2.1 Clocking Scheme

      92
    • 6.2.2 Instruction Flow/Pipelining

      92
      • FIGURE 6-4: Clock/ Instruction Cycle

        92
      • EXAMPLE 6-3: Instruction Pipeline Flow

        92
    • 6.2.3 Instructions in Program Memory

      93
      • FIGURE 6-5: Instructions in Program Memory

        93
    • 6.2.4 Two-Word Instructions

      93
      • EXAMPLE 6-4: Two-Word Instructions

        93
  • 6.3 Data Memory Organization

    94
    • 6.3.1 Bank Select Register

      94
      • FIGURE 6-6: Data Memory Map for PIC18FX5K22 and PIC18FX7K22 Devices

        95
      • FIGURE 6-7: Use of the Bank Select Register (Direct Addressing)

        96
    • 6.3.2 Access Bank

      96
    • 6.3.3 General Purpose Register File

      96
    • 6.3.4 Special Function Registers

      97
      • TABLE 6-1: Special Function Register Map for PIC18F87K22 Family

        97
      • TABLE 6-2: PIC18F87K22 Family Register File Summary

        98
    • 6.3.5 STATUS Register

      104
      • Register 6-2: Status Register

        104
  • 6.4 Data Addressing Modes

    105
    • 6.4.1 Inherent and Literal Addressing

      105
    • 6.4.2 Direct Addressing

      105
    • 6.4.3 Indirect Addressing

      105
      • EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing

        105
      • FIGURE 6-8: Indirect Addressing

        106
  • 6.5 Program Memory and the Extended Instruction Set

    107
  • 6.6 Data Memory and the Extended Instruction Set

    108
    • 6.6.1 Indexed Addressing with Literal Offset

      108
    • 6.6.2 Instructions Affected By Indexed Literal Offset Mode

      108
      • FIGURE 6-9: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)

        109
    • 6.6.3 Mapping the Access Bank in Indexed Literal Offset Mode

      110
    • 6.6.4 BSR in Indexed Literal Offset Mode

      110
      • FIGURE 6-10: Remapping the Access Bank with Indexed Literal Offset Addressing

        110
• 7.0 Flash Program Memory

  111
  • 7.1 Table Reads and Table Writes

    111
    • FIGURE 7-1: Table Read Operation

      111
    • FIGURE 7-2: Table Write Operation

      112
  • 7.2 Control Registers

    112
    • 7.2.1 EECON1 and EECON2 Registers

      112
      • Register 7-1: EECON1: EEPROM Control Register 1

        113
    • 7.2.2 TABLAT – Table Latch Register

      114
    • 7.2.3 TBLPTR – Table Pointer Register

      114
    • 7.2.4 Table Pointer Boundaries

      114
      • TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions

        114
      • FIGURE 7-3: Table Pointer Boundaries Based on Operation

        114
  • 7.3 Reading the Flash Program Memory

    115
    • FIGURE 7-4: Reads From Flash Program Memory

      115
    • EXAMPLE 7-1: Reading a Flash Program Memory Word

      115
  • 7.4 Erasing Flash Program Memory

    116
    • 7.4.1 Flash Program Memory Erase Sequence

      116
      • EXAMPLE 7-2: Erasing a Flash Program Memory Row

        116
  • 7.5 Writing to Flash Program Memory

    117
    • FIGURE 7-5: Table Writes to Flash Program Memory

      117
    • 7.5.1 Flash Program Memory Write Sequence

      118
      • EXAMPLE 7-3: Writing to Flash Program Memory

        119
      • EXAMPLE 7-3: Writing to Flash Program Memory (Continued)

        120
    • 7.5.2 Write Verify

      120
    • 7.5.3 Unexpected Termination of Write Operation

      120
    • 7.5.4 Protection Against Spurious Writes

      120
  • 7.6 Flash Program Operation During Code Protection

    120
    • TABLE 7-2: Registers Associated with Program Flash Memory

      120
• 8.0 External Memory Bus

  121
  • TABLE 8-1: PIC18F87K22 family External Bus – I/O Port Functions

    121
  • 8.1 External Memory Bus Control

    122
    • Register 8-1: MEMCON: External Memory Bus Control Register(1)

      122
  • 8.2 Address and Data Width

    123
    • 8.2.1 Address Shifting on the External Bus

      123
    • 8.2.2 21-bit Addressing

      123
      • TABLE 8-2: Address and Data Lines for Different Address and Data Widths

        123
  • 8.3 Wait States

    124
  • 8.4 Port Pin Weak Pull-ups

    124
  • 8.5 Program Memory Modes and the External Memory Bus

    124
  • 8.6 16-Bit Data Width Modes

    124
    • 8.6.1 16-Bit Byte Write Mode

      125
      • FIGURE 8-1: 16-bit Byte Write Mode Example

        125
    • 8.6.2 16-Bit Word Write Mode

      126
      • FIGURE 8-2: 16-bit Word Write Mode Example

        126
    • 8.6.3 16-Bit Byte Select Mode

      127
      • FIGURE 8-3: 16-bit Byte Select Mode Example

        127
    • 8.6.4 16-Bit Mode Timing

      128
      • FIGURE 8-4: External Memory Bus Timing for TBLRD (Extended Microcontroller Mode)

        128
      • FIGURE 8-5: External Memory Bus Timing for Sleep (Extended Microcontroller Mode)

        128
  • 8.7 8-Bit Data Width Mode

    129
    • FIGURE 8-6: 8-bit Multiplexed Mode Example

      129
    • 8.7.1 8-bit Mode Timing

      130
      • FIGURE 8-7: External Memory Bus Timing For TBLRD (Extended Microcontroller Mode)

        130
      • FIGURE 8-8: External Memory Bus Timing for SLEEP (Extended Microcontroller Mode)

        130
  • 8.8 Operation in Power-Managed Modes

    131
    • TABLE 8-3: Registers Associated with the External Memory Bus

      131
• 9.0 Data EEPROM Memory

  133
  • 9.1 EEADR and EEADRH Registers

    133
  • 9.2 EECON1 and EECON2 Registers

    133
    • Register 9-1: EECON1: Data EEPROM Control Register 1

      134
  • 9.3 Reading the Data EEPROM Memory

    135
  • 9.4 Writing to the Data EEPROM Memory

    135
  • 9.5 Write Verify

    135
    • EXAMPLE 9-1: Data EEPROM Read

      136
    • EXAMPLE 9-2: Data EEPROM Write

      136
  • 9.6 Operation During Code-Protect

    137
  • 9.7 Protection Against Spurious Write

    137
  • 9.8 Using the Data EEPROM

    137
    • EXAMPLE 9-3: Data EEPROM Refresh Routine

      137
    • TABLE 9-1: Registers Associated with Data EEPROM Memory

      138
• 10.0 8 X 8 Hardware Multiplier

  139
  • 10.1 Introduction

    139
  • 10.2 Operation

    139
    • EXAMPLE 10-1: 8 x 8 Unsigned Multiply Routine

      139
    • EXAMPLE 10-2: 8 x 8 Signed Multiply Routine

      139
    • TABLE 10-1: Performance Comparison for Various Multiply Operations

      139
    • EQUATION 10-1: 16 x 16 Unsigned Multiplication Algorithm

      140
    • EXAMPLE 10-3: 16 x 16 Unsigned Multiply Routine

      140
    • EQUATION 10-2: 16 x 16 Signed Multiplication Algorithm

      140
    • EXAMPLE 10-4: 16 x 16 Signed Multiply Routine

      140
• 11.0 Interrupts

  141
  • FIGURE 11-1: PIC18F87K22 Family Interrupt Logic

    142
  • 11.1 INTCON Registers

    143
    • Register 11-1: INTCON: Interrupt Control Register

      143
    • Register 11-2: INTCON2: Interrupt Control Register 2

      144
    • Register 11-3: INTCON3: Interrupt Control Register 3

      145
  • 11.2 PIR Registers

    146
    • Register 11-4: PIR1: Peripheral Interrupt Request (Flag) Register 1

      146
    • Register 11-5: PIR2: Peripheral Interrupt Request (Flag) Register 2

      147
    • Register 11-6: PIR3: Peripheral Interrupt Request (Flag) Register 3

      148
    • Register 11-7: PIR4: Peripheral Interrupt Request (Flag) Register 4

      149
    • Register 11-8: PIR5: Peripheral Interrupt Request (Flag) Register 5

      150
    • Register 11-9: PIR6: Peripheral Interrupt Request (Flag) Register 6

      151
  • 11.3 PIE Registers

    152
    • Register 11-10: PIE1: Peripheral Interrupt Enable Register 1

      152
    • Register 11-11: PIE2: Peripheral Interrupt Enable Register 2

      153
    • Register 11-12: PIE3: Peripheral Interrupt Enable Register 3

      154
    • Register 11-13: PIE4: Peripheral Interrupt Enable Register 4

      154
    • Register 11-14: PIE5: Peripheral Interrupt Enable Register 5

      155
    • Register 11-15: PIE6: Peripheral Interrupt Enable Register 6

      156
  • 11.4 IPR Registers

    157
    • Register 11-16: IPR1: Peripheral Interrupt Priority Register 1

      157
    • Register 11-17: IPR2: Peripheral Interrupt Priority Register 2

      158
    • Register 11-18: IPR3: Peripheral Interrupt Priority Register 3

      159
    • Register 11-19: IPR4: Peripheral Interrupt Priority Register 4

      159
    • Register 11-20: IPR5: Peripheral Interrupt Priority Register 5

      160
    • Register 11-21: IPR6: Peripheral Interrupt Priority Register 6

      161
  • 11.5 RCON Register

    162
    • Register 11-22: RCON: Reset Control Register

      162
  • 11.6 INTx Pin Interrupts

    163
  • 11.7 TMR0 Interrupt

    163
  • 11.8 PORTB Interrupt-on-Change

    163
  • 11.9 Context Saving During Interrupts

    163
    • EXAMPLE 11-1: Saving STATUS, WREG and BSR Registers in RAM

      163
    • TABLE 11-1: Summary of Registers Associated with Interrupts

      164
• 12.0 I/O Ports

  165
  • FIGURE 12-1: Generic I/O Port Operation

    165
  • 12.1 I/O Port Pin Capabilities

    165
    • 12.1.1 Pin Output Drive

      165
    • 12.1.2 Pull-up Configuration

      165
      • Register 12-1: PADCFG1: Pad Configuration Register

        166
    • 12.1.3 Open-Drain Outputs

      167
      • FIGURE 12-2: Using the Open-Drain Output (USART Shown as Example)

        167
      • Register 12-2: ODCON1: Peripheral Open-Drain Control Register 1

        167
      • Register 12-3: ODCON2: Peripheral Open-Drain Control Register 2

        168
      • Register 12-4: ODCON3: Peripheral Open-Drain Control Register 3

        169
    • 12.1.4 Analog and Digital Ports

      169
  • 12.2 PORTA, TRISA and LATA Registers

    170
    • EXAMPLE 12-1: Initializing PORTA

      170
    • TABLE 12-1: PORTA Functions

      171
    • TABLE 12-2: Summary of Registers Associated with PORTA

      171
  • 12.3 PORTB, TRISB and LATB Registers

    172
    • EXAMPLE 12-2: Initializing PORTB

      172
    • TABLE 12-3: PORTB Functions

      172
    • TABLE 12-4: Summary of Registers Associated with PORTB

      173
  • 12.4 PORTC, TRISC and LATC Registers

    174
    • EXAMPLE 12-3: Initializing PORTC

      174
    • TABLE 12-5: PORTC Functions

      174
    • TABLE 12-6: Summary of Registers Associated with PORTC

      175
  • 12.5 PORTD, TRISD and LATD Registers

    176
    • EXAMPLE 12-4: Initializing PORTD

      176
    • TABLE 12-7: PORTD Functions

      176
    • TABLE 12-8: Summary of Registers Associated with PORTD

      177
  • 12.6 PORTE, TRISE and LATE Registers

    178
    • EXAMPLE 12-5: Initializing PORTE

      178
    • TABLE 12-9: PORTE Functions

      178
    • TABLE 12-10: Summary of Registers Associated with PORTE

      180
  • 12.7 PORTF, LATF and TRISF Registers

    181
    • EXAMPLE 12-6: Initializing PORTF

      181
    • TABLE 12-11: PORTF Functions

      181
    • TABLE 12-12: Summary of Registers Associated with PORTF

      182
  • 12.8 PORTG, TRISG and LATG Registers

    183
    • EXAMPLE 12-7: Initializing PORTG

      183
    • TABLE 12-13: PORTG Functions

      183
    • TABLE 12-14: Summary of Registers Associated with PORTG

      184
  • 12.9 PORTH, LATH and TRISH Registers

    185
    • EXAMPLE 12-8: Initializing PORTH

      185
    • TABLE 12-15: PORTH Functions

      185
    • TABLE 12-16: Summary of Registers Associated with PORTH

      187
  • 12.10 PORTJ, TRISJ and LATJ Registers

    187
    • EXAMPLE 12-9: Initializing PORTJ

      187
    • TABLE 12-17: PORTJ Functions

      188
    • TABLE 12-18: Summary of Registers Associated with PORTJ

      188
  • 12.11 Parallel Slave Port

    189
    • FIGURE 12-3: PORTD and PORTE Block Diagram (Parallel Slave Port)

      189
    • Register 12-5: PSPCON: Parallel Slave Port Control Register

      190
    • FIGURE 12-4: Parallel Slave Port Write Waveforms

      190
    • FIGURE 12-5: Parallel Slave Port Read Waveforms

      191
    • TABLE 12-19: Registers Associated with Parallel Slave Port

      191
• 13.0 Timer0 Module

  193
  • Register 13-1: T0CON: Timer0 Control Register

    193
  • 13.1 Timer0 Operation

    194
  • 13.2 Timer0 Reads and Writes in 16-Bit Mode

    194
    • FIGURE 13-1: Timer0 Block Diagram (8-bit Mode)

      194
    • FIGURE 13-2: Timer0 Block Diagram (16-bit Mode)

      194
  • 13.3 Prescaler

    195
    • 13.3.1 Switching Prescaler Assignment

      195
  • 13.4 Timer0 Interrupt

    195
    • TABLE 13-1: Registers Associated with Timer0

      195
• 14.0 Timer1 Module

  197
  • Register 14-1: T1CON: Timer1 Control Register

    197
  • 14.1 Timer1 Gate Control Register

    198
    • Register 14-2: T1GCON: Timer1 Gate Control Register(1)

      198
  • 14.2 Timer1 Operation

    199
  • 14.3 Clock Source Selection

    199
    • 14.3.1 INTERNAL CLOCK SOURCE

      199
    • 14.3.2 EXTERNAL CLOCK SOURCE

      199
      • TABLE 14-1: Timer1 Clock Source Selection

        199
      • Figure 14-1: Timer1 Block Diagram

        200
  • 14.4 Timer1 16-Bit Read/Write Mode

    201
  • 14.5 SOSC Oscillator

    201
    • FIGURE 14-2: External Components for the SOSC Low-Power Oscillator

      201
    • TABLE 14-2: Capacitor Selection for the Timer Oscillator(2,3,4,5)

      201
    • 14.5.1 Using SOSC as a Clock Source

      202
    • 14.5.2 SOSC Oscillator Layout Considerations

      202
      • FIGURE 14-3: Oscillator Circuit with Grounded Guard Ring

        202
  • 14.6 Timer1 Interrupt

    202
  • 14.7 Resetting Timer1 Using the ECCP Special Event Trigger

    203
  • 14.8 Timer1 Gate

    203
    • 14.8.1 TIMER1 GATE COUNT ENABLE

      203
      • TABLE 14-3: TIMER1 GATE ENABLE SELECTIONS

        203
      • FIGURE 14-4: Timer1 Gate Count Enable Mode

        204
    • 14.8.2 TIMER1 GATE SOURCE SELECTION

      204
      • TABLE 14-4: TIMER1 GATE SOURCES

        204
    • 14.8.3 TIMER1 GATE TOGGLE MODE

      205
      • FIGURE 14-5: Timer1 Gate Toggle Mode

        205
    • 14.8.4 TIMER1 GATE SINGLE PULSE MODE

      206
    • 14.8.5 TIMER1 GATE VALUE STATUS

      206
      • FIGURE 14-6: Timer1 Gate Single Pulse Mode

        206
      • FIGURE 14-7: Timer1 Gate Single Pulse and Toggle Combined Mode

        207
      • TABLE 14-5: Registers Associated with Timer1 as a Timer/Counter

        207
• 15.0 Timer2 Module

  209
  • 15.1 Timer2 Operation

    209
    • Register 15-1: T2CON: Timer2 Control Register

      209
  • 15.2 Timer2 Interrupt

    210
  • 15.3 Timer2 Output

    210
    • FIGURE 15-1: Timer2 Block Diagram

      210
    • TABLE 15-1: Registers Associated with Timer2 as a Timer/Counter

      210
• 16.0 Timer3/5/7 Modules

  211
  • Register 16-1: TxCON: Timerx Control Register

    212
  • 16.1 Timer3/5/7 Gate Control Register

    213
    • Register 16-2: TxGCON: Timerx Gate Control Register(1)

      213
    • Register 16-3: OSCCON2: Oscillator Control Register 2

      214
  • 16.2 Timer3/5/7 Operation

    215
    • Figure 16-1: TIMER3/5/7 Block Diagram

      215
  • 16.3 Timer3/5/7 16-Bit Read/Write Mode

    216
  • 16.4 Using the SOSC Oscillator as the Timer3/5/7 Clock Source

    216
  • 16.5 Timer3/5/7 Gates

    217
    • 16.5.1 TIMER3/5/7 GATE COUNT ENABLE

      217
      • TABLE 16-1: TIMER3/5/7 GATE ENABLE SELECTIONS

        217
      • FIGURE 16-2: Timer3/5/7 Gate Count Enable Mode

        217
    • 16.5.2 TIMER3/5/7 GATE SOURCE SELECTION

      218
      • TABLE 16-2: TIMER3/5/7 GATE SOURCES

        218
    • 16.5.3 TIMER3/5/7 GATE TOGGLE MODE

      218
      • FIGURE 16-3: Timer3/5/7 Gate Toggle Mode

        218
    • 16.5.4 TIMER3/5/7 GATE SINGLE PULSE MODE

      219
      • FIGURE 16-4: Timer3/5/7 Gate Single Pulse Mode

        219
      • FIGURE 16-5: Timer3/5/7 Gate Single Pulse and Toggle Combined Mode

        220
    • 16.5.5 TIMER3/5/7 GATE VALUE STATUS

      220
    • 16.5.6 TIMER3/5/7 GATE EVENT INTERRUPT

      220
  • 16.6 Timer3/5/7 Interrupt

    221
    • TABLE 16-3: Timer3/5/7 Interrupt Flag Bits

      221
    • TABLE 16-4: Timer3/5/7 Interrupt Enable Bits

      221
  • 16.7 Resetting Timer3/5/7 Using the ECCP Special Event Trigger

    221
    • TABLE 16-5: Registers Associated with Timer3/5/7 as a Timer/Counter

      222
• 17.0 Timer4/6/8/10/12 Modules

  223
  • 17.1 Timer4/6/8/10/12 Operation

    223
    • TABLE 17-1: Timer4/6/8/10/12 Flag Bits

      223
    • TABLE 17-2: Timer4/6/8/10/12 Interrupt Enable Bits

      223
    • Register 17-1: TxCON: Timerx Control Register

      224
  • 17.2 Timer4/6/8/10/12 Interrupt

    224
  • 17.3 Output of TMRx

    224
    • FIGURE 17-1: Timer4 Block Diagram

      224
    • TABLE 17-3: Registers Associated with Timer4/6/8/10/12 as a Timer/Counter

      225
• 18.0 Real-Time Clock and Calendar (RTCC)

  227
  • FIGURE 18-1: RTCC Block Diagram

    227
  • 18.1 RTCC Module Registers

    228
  • RTCC Control Registers

    228
  • RTCC Value Registers

    228
  • Alarm Value Registers

    228
    • 18.1.1 RTCC Control Registers

      229
      • Register 18-1: RTCCFG: RTCC Configuration Register(1)

        229
      • Register 18-2: RTCCAL: RTCC Calibration Register

        230
      • Register 18-3: PADCFG1: Pad Configuration Register

        230
      • Register 18-4: ALRMCFG: Alarm Configuration Register

        231
      • Register 18-5: ALRMRPT: Alarm Repeat Register

        232
    • 18.1.2 RTCVALH and RTCVALL Register Mappings

      232
      • Register 18-6: Reserved Register

        232
      • Register 18-7: Year: Year Value Register(1)

        232
      • Register 18-8: MontH: Month Value Register(1)

        233
      • Register 18-9: Day: Day Value Register(1)

        233
      • Register 18-10: Weekday: Weekday Value Register(1)

        233
      • Register 18-11: Hour: Hour Value Register(1)

        234
      • Register 18-12: MINUTE: Minute Value Register

        234
      • Register 18-13: SECOND: Second Value Register

        234
    • 18.1.3 ALRMVALH and ALRMVALL Register Mappings

      235
      • Register 18-14: ALRMMNTH: Alarm Month Value Register(1)

        235
      • Register 18-15: ALRMDAY: Alarm Day Value Register(1)

        235
      • Register 18-16: ALRMWd: Alarm Weekday Value Register(1)

        235
      • Register 18-17: ALRMHr: Alarm Hours Value Register(1)

        236
      • Register 18-18: ALRMMIN: Alarm Minutes Value Register

        236
      • Register 18-19: ALRMSEC: Alarm Seconds Value Register

        236
    • 18.1.4 RTCEN Bit Write

      237
  • 18.2 Operation

    237
    • 18.2.1 Register Interface

      237
      • FIGURE 18-2: Timer Digit Format

        237
      • FIGURE 18-3: Alarm Digit Format

        237
    • 18.2.2 Clock Source

      238
      • FIGURE 18-4: Clock Source Multiplexing

        238
    • 18.2.3 Digit Carry Rules

      238
      • TABLE 18-1: Day of Week Schedule

        238
      • TABLE 18-2: Day to Month Rollover Schedule

        238
    • 18.2.4 Leap Year

      239
    • 18.2.5 General Functionality

      239
    • 18.2.6 Safety Window for Register Reads and Writes

      239
    • 18.2.7 Write Lock

      239
      • EXAMPLE 18-1: Setting the RTCWREN Bit

        239
    • 18.2.8 Register Mapping

      239
      • TABLE 18-3: RTCVALH and RTCVALL Register Mapping

        239
      • TABLE 18-4: ALRMVAL Register Mapping

        240
    • 18.2.9 Calibration

      240
      • EQUATION 18-1: Converting Error Clock Pulses

        240
  • 18.3 Alarm

    240
    • 18.3.1 Configuring the Alarm

      240
      • FIGURE 18-5: Alarm Mask Settings

        241
    • 18.3.2 Alarm Interrupt

      241
      • FIGURE 18-6: Timer Pulse Generation

        242
  • 18.4 Sleep Mode

    242
  • 18.5 Reset

    242
    • 18.5.1 Device Reset

      242
    • 18.5.2 Power-on Reset (POR)

      242
  • 18.6 Register Maps

    243
    • TABLE 18-5: RTCC Control Registers

      243
    • TABLE 18-6: RTCC Value Registers

      243
    • TABLE 18-7: Alarm Value Registers

      243
• 19.0 Capture/Compare/PWM (CCP) Modules

  245
  • Register 19-1: CCPxCON: CCPx Control Register (CCP4-CCP10 Modules)(1)

    245
  • Register 19-2: CCPTMRS1: CCP Timer Select Register 1

    246
  • Register 19-3: CCPTMRS2: CCP Timer Select Register 2

    247
  • Register 19-4: CCPRxL: CCPx Period Low Byte Register

    248
  • Register 19-5: CCPRxH: CCPx Period High Byte Register

    248
  • 19.1 CCP Module Configuration

    249
    • 19.1.1 CCP Modules and Timer Resources

      249
      • TABLE 19-1: CCP Mode – Timer Resource

        249
      • TABLE 19-2: Timer Assignments for CCP Modules 4, 5, 6 and 7

        249
      • TABLE 19-3: Timer Assignments for CCP Modules 8, 9 and 10

        249
    • 19.1.2 Open-Drain Output Option

      250
    • 19.1.3 Pin Assignment For CCP6, CCP7, CCP8 and CCP9

      250
      • TABLE 19-4: CCP Pin Assignment

        250
  • 19.2 Capture Mode

    250
    • 19.2.1 CCP Pin Configuration

      250
    • 19.2.2 Timer1/3/5/7 Mode Selection

      250
      • FIGURE 19-1: Capture Mode Operation Block Diagram

        251
    • 19.2.3 Software Interrupt

      251
    • 19.2.4 CCP Prescaler

      251
      • EXAMPLE 19-1: Changing Between Capture Prescalers

        251
  • 19.3 Compare Mode

    252
    • 19.3.1 CCP Pin Configuration

      252
    • 19.3.2 Timer1/3/5/7 Mode Selection

      252
    • 19.3.3 Software Interrupt Mode

      252
    • 19.3.4 Special Event Trigger

      252
      • FIGURE 19-2: Compare Mode Operation Block Diagram

        253
      • TABLE 19-5: Registers Associated with Capture, Compare, Timer1/3/5/7

        253
  • 19.4 PWM Mode

    255
    • FIGURE 19-3: Simplified PWM Block Diagram

      255
    • FIGURE 19-4: PWM Output

      255
    • 19.4.1 PWM Period

      255
      • EQUATION 19-1:

        255
    • 19.4.2 PWM Duty Cycle

      256
      • EQUATION 19-2:

        256
      • EQUATION 19-3:

        256
      • TABLE 19-6: Example PWM Frequencies and Resolutions at 40 MHz

        256
    • 19.4.3 Setup for PWM Operation

      256
      • TABLE 19-7: Registers Associated with PWM and Timers

        256
• 20.0 Enhanced Capture/Compare/PWM (ECCP) Module

  259
  • Register 20-1: CCPxCON: Enhanced Capture/Compare/PWMx Control

    260
  • Register 20-2: CCPTMRS0: CCP Timer Select 0 Register

    261
  • 20.1 ECCP Outputs and Configuration

    262
    • 20.1.1 ECCP Module and Timer Resources

      262
      • TABLE 20-1: ECCP Mode – Timer Resource

        262
    • 20.1.2 ECCP Pin Assignment

      262
  • 20.2 Capture Mode

    263
    • TABLE 20-2: ECCP1/2/3 Interrupt Flag Bits

      263
    • 20.2.1 ECCP Pin Configuration

      263
    • 20.2.2 Timer1/2/3/4/6/8/10/12 Mode Selection

      263
    • 20.2.3 Software Interrupt

      263
    • 20.2.4 ECCP Prescaler

      263
      • EXAMPLE 20-1: Changing Between Capture Prescalers

        263
      • FIGURE 20-1: Capture Mode Operation Block Diagram

        263
  • 20.3 Compare Mode

    264
    • 20.3.1 ECCP Pin Configuration

      264
    • 20.3.2 Timer1/2/3/4/6/8/10/12 Mode Selection

      264
    • 20.3.3 Software Interrupt Mode

      264
    • 20.3.4 Special Event Trigger

      264
      • FIGURE 20-2: Compare Mode Operation Block Diagram

        264
  • 20.4 PWM (Enhanced Mode)

    265
    • FIGURE 20-3: Example Simplified Block Diagram of the Enhanced PWM Mode

      265
    • TABLE 20-3: Example Pin Assignments for Various PWM Enhanced Modes

      266
    • FIGURE 20-4: Example PWM (enhanced Mode) Output Relationships (Active-High State)

      266
    • FIGURE 20-5: Example Enhanced PWM Output Relationships (Active-Low State)

      267
    • 20.4.1 Half-Bridge Mode

      268
      • FIGURE 20-6: Example of Half-Bridge PWM Output

        268
      • FIGURE 20-7: Example of Half-Bridge Applications

        268
    • 20.4.2 Full-Bridge Mode

      269
      • FIGURE 20-8: Example of Full-Bridge Application

        269
      • FIGURE 20-9: Example of Full-Bridge PWM Output

        270
      • FIGURE 20-10: Example of PWM Direction Change

        271
      • FIGURE 20-11: Example of PWM Direction Change at Near 100% Duty Cycle(1)

        272
    • 20.4.3 Start-up Considerations

      272
    • 20.4.4 Enhanced PWM Auto-shutdown mode

      272
      • Register 20-3: ECCPxAS: ECCPx Auto-Shutdown Control Register

        273
      • FIGURE 20-12: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)

        274
    • 20.4.5 Auto-Restart Mode

      274
      • FIGURE 20-13: PWM Auto-shutdown With Auto-Restart Enabled (PxRSEN = 1)

        274
    • 20.4.6 Programmable Dead-Band Delay Mode

      275
      • FIGURE 20-14: Example of Half-Bridge PWM Output

        275
      • FIGURE 20-15: Example of Half-Bridge Applications

        275
      • Register 20-4: ECCPxDEL: Enhanced PWM Control Register

        276
    • 20.4.7 Pulse Steering Mode

      276
      • Register 20-5: PSTRxCON: Pulse Steering Control(1)

        277
      • FIGURE 20-16: Simplified Steering Block Diagram

        278
      • FIGURE 20-17: Example of Steering Event at End of Instruction (STRSYNC = 0)

        278
      • FIGURE 20-18: Example of Steering Event at Beginning of Instruction (STRSYNC = 1)

        278
    • 20.4.8 Operation in Power-Managed Modes

      279
    • 20.4.9 Effects of a Reset

      279
      • TABLE 20-4: Registers Associated with ECCP1/2/3 Module and Timer1/2/3/4/6/8/10/12

        279
• 21.0 Master Synchronous Serial Port (MSSP) Module

  281
  • 21.1 Master SSP (MSSP) Module Overview

    281
  • 21.2 Control Registers

    281
  • 21.3 SPI Mode

    281
    • FIGURE 21-1: MSSP Block Diagram (SPI Mode)

      281
    • 21.3.1 Registers

      282
      • Register 21-1: SSPxSTAT: MSSPx Status Register (SPI Mode)

        282
      • Register 21-2: SSPxCON1: MSSPx Control Register 1 (SPI Mode)

        283
    • 21.3.2 Operation

      284
    • 21.3.3 OPEN-DRAIN OUTPUT OPTION

      284
      • EXAMPLE 21-1: Loading the SSP1BUF (SSP1SR) Register

        284
    • 21.3.4 Enabling SPI I/O

      285
    • 21.3.5 Typical Connection

      285
      • FIGURE 21-2: SPI Master/Slave Connection

        285
    • 21.3.6 Master Mode

      286
      • FIGURE 21-3: SPI Mode Waveform (Master Mode)

        286
    • 21.3.7 Slave Mode

      287
    • 21.3.8 Slave Select Synchronization

      287
      • FIGURE 21-4: Slave Synchronization Waveform

        287
      • FIGURE 21-5: SPI Mode Waveform (Slave Mode with CKE = 0)

        288
      • FIGURE 21-6: SPI Mode Waveform (Slave Mode with CKE = 1)

        288
    • 21.3.9 Operation in Power-Managed Modes

      289
    • 21.3.10 Effects of a Reset

      289
    • 21.3.11 Bus Mode Compatibility

      289
      • TABLE 21-1: SPI Bus Modes

        289
    • 21.3.12 SPI Clock Speed and Module Interactions

      289
      • TABLE 21-2: Registers Associated with SPI Operation

        290
  • 21.4 I2C Mode

    291
    • FIGURE 21-7: MSSP Block Diagram (I2C™ Mode)

      291
    • 21.4.1 Registers

      291
      • Register 21-3: SSPxSTAT: MSSPx Status Register (I2C™ Mode)

        292
      • Register 21-4: SSPxCON1: MSSPx Control Register 1 (I2C™ Mode)

        293
      • Register 21-5: SSPxCON2: MSSPx Control Register 2 (I2C™ Master Mode)

        294
      • Register 21-6: SSPxCON2: MSSPx Control Register 2 (I2C™ Slave Mode)

        295
      • Register 21-7: SSPxMSK: I2C™ Slave Address Mask Register (7-bit Masking Mode)(1)

        295
    • 21.4.2 Operation

      296
    • 21.4.3 Slave Mode

      296
      • EXAMPLE 21-2: Address Masking Examples in 5-bit Masking Mode

        297
      • EXAMPLE 21-3: Address Masking Examples in 7-Bit Masking Mode

        298
      • FIGURE 21-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)

        300
      • FIGURE 21-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Address)

        301
      • FIGURE 21-10: I2C™ Slave Mode Timing (Transmission, 7-bit Address)

        302
      • FIGURE 21-11: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Address)

        303
      • FIGURE 21-12: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)

        304
      • FIGURE 21-13: I2C™ Slave Mode Timing (Transmission, 10-bit Address)

        305
    • 21.4.4 Clock Stretching

      306
      • FIGURE 21-14: Clock Synchronization Timing

        307
      • FIGURE 21-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)

        308
      • FIGURE 21-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)

        309
    • 21.4.5 General Call Address Support

      310
      • FIGURE 21-17: Slave Mode General Call Address Sequence (7 or 10-bit Addressing Mode)

        310
    • 21.4.6 Master Mode

      311
      • FIGURE 21-18: MSSP Block Diagram (I2C™ Master Mode)

        311
    • 21.4.7 Baud Rate

      313
      • FIGURE 21-19: Baud Rate Generator Block Diagram

        313
      • TABLE 21-3: I2C™ Clock Rate w/BRG

        313
      • FIGURE 21-20: Baud Rate Generator Timing with Clock Arbitration

        314
    • 21.4.8 I2C™ Master Mode Start Condition Timing

      315
      • FIGURE 21-21: First Start Bit Timing

        315
    • 21.4.9 I2C™ Master Mode Repeated Start Condition Timing

      316
      • FIGURE 21-22: Repeated Start Condition Waveform

        316
    • 21.4.10 I2C™ Master Mode Transmission

      317
    • 21.4.11 I2C™ Master Mode Reception

      317
      • FIGURE 21-23: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Address)

        318
      • FIGURE 21-24: I2C™ Master Mode Waveform (Reception, 7-bit Address)

        319
    • 21.4.12 Acknowledge Sequence Timing

      320
    • 21.4.13 Stop Condition Timing

      320
      • FIGURE 21-25: Acknowledge Sequence Waveform

        320
      • FIGURE 21-26: Stop Condition Receive or Transmit Mode

        320
    • 21.4.14 Sleep Operation

      321
    • 21.4.15 Effects of a Reset

      321
    • 21.4.16 Multi-master Mode

      321
    • 21.4.17 Multi -master Communication, Bus Collision and Bus Arbitration

      321
      • FIGURE 21-27: Bus Collision Timing for Transmit and Acknowledge

        321
      • FIGURE 21-28: Bus Collision During Start Condition (SDAx Only)

        322
      • FIGURE 21-29: Bus Collision During Start Condition (SCLx = 0)

        323
      • FIGURE 21-30: BRG Reset Due to SDAx Arbitration During Start Condition

        323
      • FIGURE 21-31: Bus Collision During a Repeated Start Condition (Case 1)

        324
      • FIGURE 21-32: Bus Collision During Repeated Start Condition (Case 2)

        324
      • FIGURE 21-33: Bus Collision During a Stop Condition (Case 1)

        325
      • FIGURE 21-34: Bus Collision During a Stop Condition (Case 2)

        325
      • TABLE 21-4: Registers Associated with I2C™ Operation

        326
• 22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

  327
  • Register 22-1: TXSTAx: Transmit Status And Control Register

    328
  • Register 22-2: RCSTAx: Receive Status And Control Register

    329
  • Register 22-3: BAUDCONx: Baud Rate Control Register

    330
  • 22.1 Baud Rate Generator (BRG)

    331
    • 22.1.1 Operation in Power-Managed Modes

      331
    • 22.1.2 Sampling

      331
      • TABLE 22-1: Baud Rate Formulas

        331
      • EXAMPLE 22-1: Calculating Baud Rate Error

        332
      • TABLE 22-2: Registers Associated with Baud Rate Generator

        332
      • TABLE 22-3: Baud Rates for Asynchronous Modes

        333
    • 22.1.3 Auto-Baud Rate Detect

      335
      • TABLE 22-4: BRG Counter Clock Rates

        335
      • FIGURE 22-1: Automatic Baud Rate Calculation

        336
      • FIGURE 22-2: BRG Overflow Sequence

        336
  • 22.2 EUSART Asynchronous Mode

    337
    • 22.2.1 EUSART Asynchronous Transmitter

      337
      • FIGURE 22-3: EUSART Transmit Block Diagram

        338
      • FIGURE 22-4: Asynchronous Transmission

        338
      • FIGURE 22-5: Asynchronous Transmission (Back-to-Back)

        338
      • TABLE 22-5: Registers Associated with Asynchronous Transmission

        339
    • 22.2.2 EUSART Asynchronous Receiver

      340
    • 22.2.3 Setting Up 9-bit Mode with Address Detect

      340
      • FIGURE 22-6: EUSART Receive Block Diagram

        340
      • FIGURE 22-7: Asynchronous Reception

        341
      • TABLE 22-6: Registers Associated with Asynchronous Reception

        341
    • 22.2.4 Auto-Wake-up on Sync Break Character

      342
      • FIGURE 22-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation

        343
      • FIGURE 22-9: Auto-Wake-up Bit (WUE) Timings During Sleep

        343
    • 22.2.5 Break Character Sequence

      344
    • 22.2.6 Receiving A Break Character

      344
      • FIGURE 22-10: Send Break Character Sequence

        344
  • 22.3 EUSART Synchronous Master Mode

    345
    • 22.3.1 EUSART Synchronous Master Transmission

      345
      • FIGURE 22-11: Synchronous Transmission

        345
      • FIGURE 22-12: Synchronous Transmission (Through TXEN)

        346
      • TABLE 22-7: Registers Associated with Synchronous Master Transmission

        346
    • 22.3.2 EUSART Synchronous Master Reception

      347
      • FIGURE 22-13: Synchronous Reception (Master Mode, SREN)

        347
      • TABLE 22-8: Registers Associated with Synchronous Master Reception

        348
  • 22.4 EUSART Synchronous Slave Mode

    349
    • 22.4.1 EUSART Synchronous Slave Transmission

      349
      • TABLE 22-9: Registers Associated with Synchronous Slave Transmission

        349
    • 22.4.2 EUSART Synchronous Slave Reception

      350
      • TABLE 22-10: Registers Associated with Synchronous Slave Reception

        350
• 23.0 12-Bit Analog-to-Digital Converter (A/D) Module

  351
  • 23.1 Differential A/D Converter

    351
    • FIGURE 23-1: Differential Channel Measurement

      351
    • FIGURE 23-2: Single Channel Measurement

      351
  • 23.2 A/D Registers

    352
    • 23.2.1 A/D Control Registers

      352
      • Register 23-1: ADCON0: A/D Control Register 0

        352
      • Register 23-2: ADCON1: A/D Control Register 1

        353
      • Register 23-3: ADCON2: A/D Control Register 2

        354
    • 23.2.2 A/D Result Registers

      355
      • FIGURE 23-3: A/D Result Justification

        355
      • Register 23-4: ADRESH: A/D Result High Byte Register, Left Justified (ADFM = 0)

        356
      • Register 23-5: ADRESL: A/D Result High Byte Register, Left Justified (ADFM = 0)

        356
      • Register 23-6: ADRESH: A/D Result High Byte Register, Right Justified (ADFM = 1)

        357
      • Register 23-7: ADRESL: A/D Result Low Byte Register, Right Justified (ADFM = 1)

        357
      • Register 23-8: ANCON0: A/D Port Configuration Register 0

        358
      • Register 23-9: ANCON1: A/D Port Configuration Register 1

        358
      • Register 23-10: ANCON2: A/D Port Configuration Register 2

        359
      • FIGURE 23-4: A/D Block Diagram

        360
      • FIGURE 23-5: Analog Input Model

        361
  • 23.3 A/D Acquisition Requirements

    362
    • EQUATION 23-1: Acquisition Time

      362
    • EQUATION 23-2: A/D Minimum Charging Time

      362
    • EQUATION 23-3: Calculating the Minimum Required Acquisition Time

      362
  • 23.4 Selecting and Configuring Automatic Acquisition Time

    363
  • 23.5 Selecting the A/D Conversion Clock

    363
    • TABLE 23-1: Tad vs. Device Operating Frequencies

      363
  • 23.6 Configuring Analog Port Pins

    363
  • 23.7 A/D Conversions

    364
    • FIGURE 23-6: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)

      364
    • FIGURE 23-7: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)

      364
  • 23.8 Use of the Special Event Triggers

    365
  • 23.9 Operation in Power-Managed Modes

    365
    • TABLE 23-2: Registers Associated with A/D Module

      366
• 24.0 Comparator Module

  367
  • 24.1 Registers

    367
    • FIGURE 24-1: Comparator Simplified Block Diagram

      367
    • Register 24-1: CMxCON: Comparator Control x Register

      368
    • Register 24-2: CMSTAT: Comparator Status Register

      369
  • 24.2 Comparator Operation

    370
    • FIGURE 24-2: Single Comparator

      370
  • 24.3 Comparator Response Time

    370
  • 24.4 Analog Input Connection Considerations

    370
    • FIGURE 24-3: Comparator Analog Input Model

      370
  • 24.5 Comparator Control and Configuration

    371
    • TABLE 24-1: Comparator Inputs and Outputs

      371
    • 24.5.1 Comparator Enable and Input selection

      371
    • 24.5.2 Comparator Enable and OUtput Selection

      371
      • FIGURE 24-4: Comparator Configurations

        372
  • 24.6 Comparator Interrupts

    373
    • TABLE 24-2: Comparator Interrupt Generation

      373
  • 24.7 Comparator Operation During Sleep

    374
  • 24.8 Effects of a Reset

    374
    • TABLE 24-3: Registers Associated with Comparator Module

      374
• 25.0 Comparator Voltage Reference Module

  375
  • 25.1 Configuring the Comparator Voltage Reference

    375
    • EQUATION 25-1:

      375
    • Register 25-1: CVRCON: Comparator Voltage Reference Control Register

      375
    • FIGURE 25-1: Comparator Voltage Reference Block Diagram

      376
  • 25.2 Voltage Reference Accuracy/Error

    376
  • 25.3 Operation During Sleep

    376
  • 25.4 Effects of a Reset

    376
  • 25.5 Connection Considerations

    376
    • FIGURE 25-2: Comparator Voltage Reference Output Buffer Example

      377
    • TABLE 25-1: Registers Associated with Comparator Voltage Reference

      377
• 26.0 High/Low-Voltage Detect (HLVD)

  379
  • Register 26-1: HLVDCON: High/Low-Voltage Detect Control Register

    379
  • 26.1 Operation

    380
    • FIGURE 26-1: HLVD Module Block Diagram (with External Input)

      380
  • 26.2 HLVD Setup

    381
  • 26.3 Current Consumption

    381
  • 26.4 HLVD Start-up Time

    381
    • FIGURE 26-2: Low-Voltage Detect Operation (VDIRMAG = 0)

      382
    • FIGURE 26-3: High-Voltage Detect Operation (VDIRMAG = 1)

      383
  • 26.5 Applications

    383
    • FIGURE 26-4: Typical Low-Voltage Detect Application

      383
  • 26.6 Operation During Sleep

    384
  • 26.7 Effects of a Reset

    384
    • TABLE 26-1: Registers Associated with High/Low-Voltage Detect Module

      384
• 27.0 Charge Time Measurement Unit (CTMU)

  385
  • FIGURE 27-1: CTMU Block Diagram

    385
  • 27.1 CTMU Registers

    386
    • Register 27-1: CTMUCONH: CTMU Control High Register

      386
    • Register 27-2: CTMUCONL: CTMU Control Low Register

      387
    • Register 27-3: CTMUICON: CTMU current Control Register

      388
  • 27.2 CTMU Operation

    389
    • 27.2.1 Theory of Operation

      389
    • 27.2.2 Current Source

      389
    • 27.2.3 Edge Selection and Control

      389
    • 27.2.4 Edge Status

      389
    • 27.2.5 Interrupts

      390
  • 27.3 CTMU Module Initialization

    390
  • 27.4 Calibrating the CTMU Module

    390
    • 27.4.1 Current Source Calibration

      390
      • FIGURE 27-2: CTMU Current Source Calibration Circuit

        391
      • EXAMPLE 27-1: Setup for CTMU Calibration Routines

        392
      • EXAMPLE 27-2: Current Calibration Routine

        393
    • 27.4.2 Capacitance Calibration

      394
      • EXAMPLE 27-3: Capacitance Calibration Routine

        395
  • 27.5 Measuring Capacitance with the CTMU

    396
    • 27.5.1 Absolute Capacitance Measurement

      396
    • 27.5.2 Relative Charge Measurement

      396
      • EXAMPLE 27-4: Routine for Capacitive Touch Switch

        397
  • 27.6 Measuring Time with the CTMU Module

    398
    • FIGURE 27-3: Typical Connections and Internal Configuration for Time Measurement

      398
  • 27.7 Creating a Delay with the CTMU Module

    399
    • FIGURE 27-4: Typical Connections and Internal Configuration for Pulse Delay Generation

      399
  • 27.8 Measuring Temperature with the CTMU Module

    400
    • EXAMPLE 27-5: Routine for Temperature Measurement Using Internal Diode

      400
  • 27.9 Operation During Sleep/Idle Modes

    401
    • 27.9.1 Sleep Mode

      401
    • 27.9.2 Idle Mode

      401
  • 27.10 Effects of a Reset on CTMU

    401
    • TABLE 27-1: Registers Associated with CTMU Module

      401
• 28.0 Special Features of the CPU

  403
  • 28.1 Configuration Bits

    403
    • TABLE 28-1: Configuration Bits and Device IDs

      404
    • Register 28-1: CONFIG1L: Configuration Register 1 lOW (Byte Address 300000h)

      405
    • Register 28-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)

      406
    • Register 28-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)

      407
    • Register 28-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)

      408
    • Register 28-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)

      409
    • Register 28-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)

      410
    • Register 28-7: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)

      411
    • Register 28-8: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)

      412
    • Register 28-9: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)

      413
    • Register 28-10: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)

      414
    • Register 28-11: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)

      415
    • Register 28-12: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)

      416
    • Register 28-13: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)

      417
    • Register 28-14: DEVID1: Device ID Register 1 for the PIC18F87K22 Family

      418
    • Register 28-15: DEVID2: Device ID Register 2 for the PIC18F87K22 Family

      418
  • 28.2 Watchdog Timer (WDT)

    419
    • FIGURE 28-1: WDT Block Diagram

      419
    • 28.2.1 Control Register

      420
      • Register 28-16: WDTCON: Watchdog Timer Control Register

        420
      • TABLE 28-2: Summary of Watchdog Timer Registers

        420
  • 28.3 On-Chip Voltage Regulator

    421
    • 28.3.1 Regulator Enable/Disable By Hardware

      421
      • FIGURE 28-2: Connections for the On-chip Regulator

        421
    • 28.3.2 Operation of Regulator in Sleep

      422
      • TABLE 28-3: Sleep Mode Regulator Settings(1)

        422
  • 28.4 Two-Speed Start-up

    423
    • 28.4.1 Special Considerations for Using Two-Speed Start-up

      423
      • FIGURE 28-3: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)

        423
  • 28.5 Fail-Safe Clock Monitor

    424
    • FIGURE 28-4: FSCM Block Diagram

      424
    • 28.5.1 FSCM and the Watchdog Timer

      424
    • 28.5.2 Exiting Fail-Safe Operation

      424
      • FIGURE 28-5: FSCM Timing Diagram

        425
    • 28.5.3 FSCM Interrupts in Power-Managed Modes

      425
    • 28.5.4 POR or Wake From Sleep

      425
  • 28.6 Program Verification and Code Protection

    426
    • FIGURE 28-6: Code-Protected Program Memory for the PIC18F87K22 Family(1)

      426
    • TABLE 28-4: Summary of Code Protection Registers

      427
    • 28.6.1 Program Memory Code Protection

      427
      • FIGURE 28-7: Table Write (WRTx) Disallowed

        427
      • FIGURE 28-8: External Block Table Read (EBTRx) Disallowed

        428
      • FIGURE 28-9: External Block Table Read (EBTRx) Allowed

        428
    • 28.6.2 Data EEPROM Code Protection

      429
    • 28.6.3 Configuration Register Protection

      429
  • 28.7 ID Locations

    429
  • 28.8 In-Circuit Serial Programming

    429
  • 28.9 In-Circuit Debugger

    429
    • TABLE 28-5: Debugger Resources

      429
• 29.0 Instruction Set Summary

  431
  • 29.1 Standard Instruction Set

    431
    • TABLE 29-1: Opcode Field Descriptions

      432
    • FIGURE 29-1: General Format for Instructions

      433
    • TABLE 29-2: PIC18F87K22 Family Instruction Set

      434
    • 29.1.1 Standard Instruction Set

      437
  • 29.2 Extended Instruction Set

    473
    • 29.2.1 Extended Instruction Syntax

      473
      • TABLE 29-3: Extensions to the PIC18 Instruction Set

        473
    • 29.2.2 Extended Instruction Set

      474
    • 29.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode

      478
    • 29.2.4 Considerations When Enabling the Extended Instruction Set

      478
    • 29.2.5 Special Considerations with Microchip MPLAB® IDE Tools

      480
  • 30.0 Development Support

    481
• 31.0 Electrical Characteristics

  485
  • Absolute Maximum Ratings(†)

    485
    • FIGURE 31-1: Voltage-frequency Graph, Regulator Enabled (Industrial/Extended)(1)

      486
    • FIGURE 31-2: Voltage-frequency Graph, Regulator Disabled (Industrial/Extended)(1,2)

      486
  • 31.1 DC Characteristics: Supply Voltage PIC18F87K22 Family (Industrial/Extended)

    487
  • 31.2 DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended)

    488
  • 31.3 DC Characteristics: PIC18F87K22 Family (Industrial/Extended)

    497
  • 31.4 DC Characteristics: CTMU Current Source Specifications

    498
    • TABLE 31-1: Memory Programming Requirements

      499
    • TABLE 31-2: Comparator Specifications

      500
    • TABLE 31-3: Voltage Reference Specifications

      500
    • TABLE 31-4: Internal Voltage Regulator Specifications

      500
  • 31.5 AC (Timing) Characteristics

    501
    • 31.5.1 Timing Parameter Symbology

      501
    • 31.5.2 Timing Conditions

      502
      • TABLE 31-5: Temperature and Voltage Specifications – AC

        502
      • FIGURE 31-3: Load Conditions for Device Timing Specifications

        502
    • 31.5.3 Timing Diagrams and Specifications

      503
      • FIGURE 31-4: External Clock Timing

        503
      • TABLE 31-6: External Clock Timing Requirements

        503
      • TABLE 31-7: PLL Clock Timing Specifications (Vdd = 1.8V to 5.5V)

        504
      • TABLE 31-8: Internal RC Accuracy (INTOSC)

        504
      • FIGURE 31-5: CLKO and I/O Timing

        505
      • TABLE 31-9: CLKO and I/O Timing Requirements

        505
      • FIGURE 31-6: Program Memory Fetch Timing Diagram (8-Bit)

        506
      • TABLE 31-10: Program Memory Fetch Timing Requirements (8-Bit)

        506
      • FIGURE 31-7: Program Memory Read Timing Diagram

        507
      • TABLE 31-11: CLKO and I/O Timing Requirements

        507
      • FIGURE 31-8: Program Memory Write Timing Diagram

        508
      • TABLE 31-12: Program Memory Write Timing Requirements

        508
      • FIGURE 31-9: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

        509
      • FIGURE 31-10: Brown-out Reset Timing

        509
      • TABLE 31-13: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements

        510
      • FIGURE 31-11: High/Low-Voltage Detect Characteristics

        511
      • TABLE 31-14: High/Low-Voltage Detect Characteristics

        511
      • FIGURE 31-12: Timer0 and Timer1 External Clock Timings

        512
      • TABLE 31-15: Timer0 and Timer1 External Clock Requirements

        512
      • FIGURE 31-13: Capture/Compare/PWM Timings (ECCP1, ECCP2 Modules)

        513
      • TABLE 31-16: Capture/Compare/PWM Requirements (ECCP1, ECCP2 Modules)

        513
      • FIGURE 31-14: Example SPI Master Mode Timing (CKE = 0)

        514
      • TABLE 31-17: Example SPI Mode Requirements (Master Mode, Cke = 0)

        514
      • FIGURE 31-15: Example SPI Master Mode Timing (CKE = 1)

        515
      • TABLE 31-18: Example SPI Mode Requirements (Master Mode, CKE = 1)

        515
      • FIGURE 31-16: Example SPI Slave Mode Timing (CKE = 0)

        516
      • TABLE 31-19: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)

        516
      • FIGURE 31-17: Example SPI Slave Mode Timing (CKE = 1)

        517
      • TABLE 31-20: Example SPI Slave Mode Requirements (CKE = 1)

        517
      • FIGURE 31-18: I2C™ Bus Start/Stop Bits Timing

        518
      • TABLE 31-21: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)

        518
      • FIGURE 31-19: I2C™ Bus Data Timing

        519
      • TABLE 31-22: I2C™ Bus Data Requirements (Slave Mode)

        519
      • FIGURE 31-20: MSSP I2C™ Bus Start/Stop Bits Timing Waveforms

        520
      • TABLE 31-23: MSSP I2C™ Bus Start/Stop Bits Requirements

        520
      • FIGURE 31-21: MSSP I2C™ Bus Data Timing

        520
      • TABLE 31-24: MSSP I2C™ Bus Data Requirements

        521
      • FIGURE 31-22: EUSART Synchronous Transmission (Master/Slave) Timing

        522
      • TABLE 31-25: EUSART/AUSART Synchronous Transmission Requirements

        522
      • FIGURE 31-23: EUSART/AUSART Synchronous Receive (Master/Slave) Timing

        522
      • TABLE 31-26: EUSART/AUSART Synchronous Receive Requirements

        522
      • TABLE 31-27: A/D Converter Characteristics: PIC18F87K22 Family (Industrial)

        523
      • FIGURE 31-24: A/D Conversion Timing

        524
      • TABLE 31-28: A/D Conversion Requirements

        524
• 32.0 Packaging Information

  525
  • 32.1 Package Marking Information

    525
  • 32.2 Package Details

    526
• Appendix A: Revision History

  533
  • Revision A (November 2009)

    533
  • Revision B (May 2010)

    533
  • Revision C (March 2011)

    533
  • Revision D (June 2011)

    533
• Appendix B: Migration From PIC18F87J11 and PIC18F8722 to PIC18F87K22

  534
  • TABLE B-1: Notable Differences Between PIC18F87K22, PIC18F87J11 and PIC18F8722 Families

    534
• INDEX

  535
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  547
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  547
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  547
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  548
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  549
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  550