Samsung M393B5670EH1-CF8 マニュアル

目次

• 1.0 DDR3 Registered DIMM Ordering Information

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• 2.0 Key Features

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• 3.0 Address Configuration

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• 4.0 Registered DIMM Pin Configurations (Front side/Back side)

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• 5.0 Pin Description

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• 6.0 ON DIMM Thermal Sensor

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• 7.0 Input/Output Functional Description

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• 8.0 Pinout comparison Based on Module Type

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• 9.0 Registering Clock Driver Specification

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  • 9.1 Timing & Capacitance values

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  • 9.2 Clock driver Characteristics

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• 10.0 Functional Block Diagram:

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  • 10.1 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

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  • 10.2 2GB, 256Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

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  • 10.3 2GB, 256Mx72 module (Populated as 1 rank of x4 DDR3 SDRAMs)

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  • 10.4 4GB, 512Mx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)

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  • 10.5 4GB, 512Mx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs)

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  • 10.6 8GB, 1Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs)

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• 11.0 Absolute Maximum Ratings

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  • 11.1 Absolute Maximum DC Ratings

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  • 11.2 DRAM Component Operating Temperature Range

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• 12.0 AC & DC Operating Conditions

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  • 12.1 Recommended DC Operating Conditions (SSTL - 15)

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• 13.0 AC & DC Input Measurement Levels

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  • 13.1 AC & DC Logic Input Levels for Single-ended Signals

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  • 13.2 VREF Tolerances

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  • 13.3 AC and DC Logic Input Levels for Differential Signals

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    • 13.3.1 Differential Signals Definition

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    • 13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

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    • 13.3.3 Single-ended Requirements for Differential Signals

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    • 13.3.4 Differential Input Cross Point Voltage

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  • 13.4 Slew Rate Definition for Single Ended Input Signals

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  • 13.5 Slew Rate Definition for Differential Input Signals

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• 14.0 AC and DC Output Measurement Levels

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  • 14.1 Single Ended AC and DC Output Levels

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  • 14.2 Differential AC and DC Output Levels

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  • 14.3 Single Ended Output Slew Rate

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  • 14.4 Differential Output Slew Rate

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• 15.0 IDD specification definition

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  • 15.1 IDD SPEC Table

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• 16.0 Input/Output Capacitance

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• 17.0 Electrical Characteristics and AC timing

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  • 17.1 Refresh Parameters by Device Density

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  • 17.2 Speed Bins and CL, tRCD, tRC and tRAS for Corresponding Bin

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  • 17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

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    • 17.3.1 Speed Bin Table Notes

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• 18.0 Timing Parameters for DDR3-800, DDR3-1066 and DDR3-1333

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  • 18.1 Jitter Notes

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  • 18.2 Timing Parameter Notes

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• 19.0 Physical Dimensions :

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  • 19.1 128Mbx8 based 128Mx72 Module(1 Rank) - M393B2873EH1

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    • 19.1.1 x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs

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  • 19.2 128Mbx8 based 256Mx72 Module(2 Ranks) - M393B5673EH1

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    • 19.2.1 x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs

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  • 19.3 256Mbx4 based 256Mx72 Module(1 Rank) - M393B5670EH1

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    • 19.3.1 x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs

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  • 19.4 256Mbx4 based 512Mx72 Module(2 Ranks) - M393B5170EH1

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    • 19.4.1 x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs

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    • 19.4.2 Heat Spreader Design Guide

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  • 19.5 128Mbx8 based 512Mx72 Module(4 Ranks) - M393B5173EH1

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    • 19.5.1 x72 DIMM, populated as four physical ranks of x8 DDR3 SDRAMs

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  • 19.6 512Mbx4 based 1Gx72 Module(4 Ranks) - M393B1G70EM1

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    • 19.6.1 x72 DIMM, populated as four physical ranks of x4 DDR3 SDRAMs

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    • 19.6.2 Heat Spreader Design Guide

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