SMSC LAN1198 マニュアル

目次

• 1 Introduction

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  • 1.1 References

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  • 1.2 Document Conventions

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• 2 Controller Overview

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  • 2.1 Block Diagrams

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    • 2.1.1 Internal Block Diagram

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      • Figure 2.1 LAN9118 Family Device Internal Block Diagram

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    • 2.1.2 System Level Block Diagram

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      • Figure 2.2 LAN9118 Family Device System-Level Block-Diagram

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  • 2.2 Common Product Family Features

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• 3 Register Description

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  • Figure 3.1 LAN9118 Family Device Memory MAP

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  • 3.1 Directly Addressable Registers

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    • Table 3.1 LAN9118 Family Directly Addressable Register Map

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  • 3.2 MAC Control and Status Registers

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    • Table 3.2 LAN9118 Family MAC CSR Register Map

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  • 3.3 PHY Registers

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    • Table 3.3 LAN9118 Family PHY Control and Status Register

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  • 3.4 Restrictions on Read-Follow-Write CSR Accesses

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    • Table 3.4 Read after Write Timing Rules

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  • 3.5 Restrictions on Read-Follow-Read CSR Accesses

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    • Table 3.5 Special Back-to-Back Cycles

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• 4 Programming Recommendations

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  • 4.1 The Necessity of Register Ownership

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  • 4.2 The Importance of Planning (strcmp(“Fail to Plan”) == strcmp (“Plan to Fail”))

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  • 4.3 Orthogonal Register Set

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  • 4.4 Register Functionality in the LAN9118 Family Devices

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    • Table 4.1 Independent Data Threads Register Usage

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  • 4.5 An Example of Concurrency

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  • 4.6 Software Interrupt Feature (SwInt)

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  • 4.7 Ownership Policy in the Simple Driver

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    • Table 4.2 Register Ownership Policy in the Simple Driver

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• 5 Initialization

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  • 5.1 MAC Initialization

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    • 5.1.1 Software Reset of the MAC

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    • 5.1.2 FIFO Allocation and Flow-Control Configuration

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    • 5.1.3 Setting the MAC Address

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      • Table 5.1 EEPROM MAC Address Layout

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  • 5.2 Configuring Interrupts

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    • 5.2.1 Configuring the IRQ Pin

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    • 5.2.2 Setting The Interrupt De-assertion Period

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    • 5.2.3 Enabling and Disabling Interrupts

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  • 5.3 Stopping and Starting the Transmitter

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  • 5.4 Stopping and Starting the Receiver

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  • 5.5 Configuring Address Filtering Options

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    • Table 5.2 Address Filtering Modes

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    • 5.5.1 Configuring Multicast Filtering

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    • 5.5.2 Promiscuous Mode

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  • 5.6 PHY Detection and Initialization

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    • Table 5.3 Using the MAC_CSR_CMD Register to Access the MII_ACC Register

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    • Table 5.4 Using the MAC_CSR_CMD Register to Access the MII_DATA Register

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    • Table 5.5 Media Independent Interface Access/Command Register

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    • Figure 5.1 PHY Access Command and Data Pathways

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  • 5.7 Switching Between Internal and External PHYs

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    • Figure 5.2 The MII Switching Procedure

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  • 5.8 Examples of PHY MII Register Reads and Writes

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• 6 Transmit Packet Processing

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  • 6.1 Transmit Data Transfer

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  • 6.2 Command Word Construction

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  • 6.3 Per Packet Flow Control

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  • 6.4 Packet Transfer Completion: Management Statistics

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    • Table 6.1 ransmit Status Word

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  • 6.5 Transmit Packet Examples

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    • Table 6.2 Transmit Packet Example

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    • Table 6.3 Buffer End Alignment

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    • Table 6.4 Transmit Command Words

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    • Table 6.5 Single Buffer Single Packet Data Transfer Sequence

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    • Figure 6.1 Multiple (3) Buffer Data Single Packet Transfer Sequence

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    • 6.5.1 Transmit Command Words for Figure 6.1, "Multiple (3) Buffer Data Single Packet Transfer Sequence"

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      • Table 6.6 TX_CMD_A for Segment 1

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      • Table 6.7 TX_CMD_B for Segment 1

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      • Table 6.8 TX_CMD_A for Segment 2

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      • Table 6.9 TX_CMD_B for Segment 2

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      • Table 6.10 TX_CMD_A for Segment 3

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      • Table 6.11 TX_CMD_B for Segment 3

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      • Table 6.12 Multiple (3) Packet Data Transfer Sequence

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  • 6.6 The Overall Packet Transmit Process

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    • Figure 6.2 Packet Transmission

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• 7 Receive Packet Processing

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  • Table 7.1 Receive Status Word

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  • Figure 7.1 Packet Reception

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  • 7.1 Receive Data Transfer

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    • Table 7.2 Receive Data Buffer Example

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    • Table 7.3 RX End Alignment

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    • Table 7.4 Receiver Configuration Word

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  • 7.2 Purging Receive Packets

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  • 7.3 Flow Control Function

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    • 7.3.1 Backpressure

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    • 7.3.2 Pause Frames

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• 8 Instrumentation and Debug

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  • 8.1 Debug Prints

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    • 8.1.1 SMSC_TRACE(message, parameters)

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    • 8.1.2 SMSC_WARNING(message, parameters)

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    • 8.1.3 SMSC_ASSERT(condition)

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  • 8.2 GPIO pins in Conjunction with Oscilloscope

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    • Figure 8.1 Oscilloscope/Logic Analyzer Display

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  • 8.3 TxCLK and RxCLK

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  • 8.4 Error Interrupts are Invaluable Tools

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  • 8.5 Integrating the Driver: Early Testing

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• 9 Power Management Events

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  • 9.1 System Description

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