STMicroelectronics FlexSPIN: SPI configurable stepper and DC multi motor driver evaluation board EVAL6460 マニュアル

目次

• Table 1. Device summary

  1
• 1 General description

  10
  • 1.1 Overview

    10
    • Figure 1. Block diagram

      10
  • 1.2 Pin connection

    11
    • Figure 2. Pin connection

      11
  • 1.3 Pin list

    12
    • Table 2. Pins configuration

      12
• 2 L6460’s main features

  14
• 3 Electrical specifications

  16
  • 3.1 Absolute maximum rating

    16
    • Table 3. Absolute maximum ratings

      16
  • 3.2 Operating ratings specifications

    16
    • Table 4. IC operating ratings

      16
  • 3.3 Electrical characteristics

    17
    • Table 5. Electrical characteristics

      17
• 4 Internal supplies

  30
  • 4.1 VSupplyInt regulator

    30
    • Figure 3. VSupplyInt pin

      30
  • 4.2 Charge pump regulator

    31
    • Figure 4. Charge pump block diagram

      31
  • 4.3 V3v3 regulator

    31
• 5 Supervisory system

  32
  • 5.1 Power on reset (POR) circuit

    32
  • 5.2 nRESET generation circuit

    32
    • Table 6. Stretch time selection

      33
    • Figure 5. nReset generation circuit

      34
  • 5.3 Thermal shut down generation circuit

    35
• 6 Watchdog circuit

  36
  • Figure 6. Watchdog circuit block diagram

    36
  • Table 7. Watchdog timeout specifications

    37
• 7 Internal clock oscillator

  38
• 8 Start-up configurations

  39
  • Table 8. Possible start-up pins state symbol

    39
  • 8.1 Operation modes

    39
    • Table 9. Start-up correspondence

      40
  • 8.2 Basic device mode

    40
  • 8.3 Slave device mode

    41
  • 8.4 Master device mode

    41
  • 8.5 Single device mode

    41
  • 8.6 Sub-configurations for slave, master or single device modes

    41
    • 8.6.1 Bridge mode

      41
    • 8.6.2 Primary regulator mode (KP)

      42
    • 8.6.3 Regulators mode

      42
    • 8.6.4 Simple regulator mode (KT)

      42
    • 8.6.5 Bridge + VEXT mode

      42
    • 8.6.6 Secondary regulators mode

      43
• 9 Power sequencing

  44
• 10 Power saving modes

  45
  • 10.1 Standby mode

    45
    • Figure 7. Standby mode function description

      45
  • 10.2 Hibernate mode

    46
  • 10.3 Low power mode

    46
  • 10.4 nAWAKE pin

    46
    • Figure 8. nAWAKE function block diagram

      47
• 11 Linear main regulator

  48
  • Figure 9. Linear main regulator

    48
  • Figure 10. Linear main regulator with external bipolar for high current

    49
• 12 Main switching regulator

  50
  • 12.1 Pulse skipping operation

    50
    • Figure 11. Main switching regulator functional blocks

      51
    • Table 10. Main switching regulator PWM specification

      51
    • Table 11. Main switching regulator current limit

      51
• 13 Switching regulator controller

  52
  • Figure 12. Switching regulator controller functional blocks

    53
  • 13.1 Pulse skipping operation

    53
    • Table 12. Switching regulator controller PWM specification

      53
  • 13.2 Output equivalent circuit

    54
    • Figure 13. Switching regulator controller output driving: equivalent circuit

      54
  • 13.3 Switching regulator controller application considerations

    54
    • Table 13. Switching regulator controller application: feedback reference

      54
• 14 Power bridges

  56
  • Figure 14. H Bridge block diagram

    56
  • Table 14. PWM selection truth table for bridge 1 or 2

    57
  • Table 15. PWM selection truth table for bridge 3 or 4

    57
  • Figure 15. Bridge 1 and 2 PWM selection

    58
  • 14.1 Possible configurations

    59
    • Table 16. Bridge selection

      59
    • Table 17. Bridge 3 and 4 configuration

      59
    • 14.1.1 Full bridge

      60
      • Table 18. Full bridge truth table

        60
    • 14.1.2 Parallel configuration (super bridge)

      61
      • Figure 16. Super bridge configuration

        61
    • 14.1.3 Half bridge configuration

      61
      • Figure 17. Half bridge configuration

        62
      • Table 19. Half bridge truth table

        62
    • 14.1.4 Switch configuration

      63
      • Table 20. Switch truth table

        63
    • 14.1.5 Bipolar stepper configuration

      63
      • Figure 18. Bipolar stepper configuration

        65
      • Table 21. Sequencer driver

        66
      • Table 22. Stepper driving mode

        66
      • Table 23. Stepper sequencer direction

        67
      • Table 24. DAC

        68
      • Table 25. Internal sequencer

        69
      • Table 26. Stepper off time

        71
      • Table 27. Stepper fast decay

        73
    • 14.1.6 Synchronous buck regulator configuration (Bridge 3)

      73
      • Figure 19. Regulator block diagram

        74
      • Table 28. PWM specification

        75
    • 14.1.7 Regulation loop

      75
      • Figure 20. Internal comparator functional block diagram

        75
    • 14.1.8 Battery charger or switching regulator (Bridge 4)

      76
      • Figure 21. Battery charger control loop block diagram

        76
      • Figure 22. Li-ion battery charge profile

        77
      • Figure 23. Simple buck regulator

        78
      • Table 29. Battery charger regulator controller PWM specification

        79
• 15 AD converter

  80
  • Figure 24. A2D block diagram

    81
  • Table 30. ADC truth table

    81
  • Table 31. Channel addresses

    82
  • Table 32. ADC sample times when working as a 8-bit ADC

    83
  • Table 33. ADC sample time when working as a 9-bit ADC

    83
  • 15.1 Voltage divider specifications

    84
    • Table 34. Voltage divider specification

      84
• 16 Current DAC circuit

  85
  • Figure 25. Current DAC block diagram

    85
  • Table 35. Current DAC truth table

    86
• 17 Operational amplifiers

  87
  • Figure 26. Configurable 3.3 V operational amplifiers

    87
• 18 Low voltage power switches

  89
  • Figure 27. Low power switch block diagram

    89
• 19 General purpose PWM

  90
  • 19.1 General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2)

    90
  • 19.2 Programmable PWM generator (GpPwm)

    90
• 20 Interrupt controller

  91
  • Figure 28. Interrupt controller diagram

    91
  • Table 36. Interrupt controller event

    91
• 21 Digital comparator

  93
  • Figure 29. Digital comparator block diagram

    94
  • Table 37. Comparison type truth table

    94
  • Table 38. DataX selection truth table

    94
• 22 GPIO pins

  95
  • Table 39. GPIO functions description

    95
  • Table 40. Abbreviations

    97
  • 22.1 GPIO[0]

    99
    • Table 41. GPIO[0] truth table

      99
    • Figure 30. GPIO[0] block diagram

      100
  • 22.2 GPIO[1]

    101
    • Table 42. GPIO[1] truth table

      101
    • Figure 31. GPIO[1] block diagram

      102
  • 22.3 GPIO[2]

    103
    • Table 43. GPIO[2] truth table

      103
    • Figure 32. GPIO[2] block diagram

      104
  • 22.4 GPIO[3]

    105
    • Table 44. GPIO[3] truth table

      105
    • Figure 33. GPIO[3] block diagram

      106
  • 22.5 GPIO[4]

    107
    • Table 45. GPIO[4] truth table

      107
    • Figure 34. GPIO[4] block diagram

      108
  • 22.6 GPIO[5]

    109
    • Table 46. GPIO[5] truth table

      109
    • Figure 35. GPIO[5] block diagram

      110
  • 22.7 GPIO[6]

    111
    • Table 47. GPIO[6] truth table

      111
    • Figure 36. GPIO[6] block diagram

      112
  • 22.8 GPIO[7]

    113
    • Table 48. GPIO[7] truth table

      113
    • Figure 37. GPIO[7] block diagram

      114
  • 22.9 GPIO[8]

    115
    • Table 49. GPIO[8] truth table

      115
    • Figure 38. GPIO[8] block diagram

      116
  • 22.10 GPIO[9]

    117
    • Table 50. GPIO[9] truth table

      117
    • Figure 39. GPIO[9] block diagram

      118
  • 22.11 GPIO[10]

    119
    • Table 51. GPIO[10] truth table

      119
    • Figure 40. GPIO[10] block diagram

      120
  • 22.12 GPIO[11]

    121
    • Table 52. GPIO[11] truth table

      121
    • Figure 41. GPIO[11] block diagram

      122
  • 22.13 GPIO[12]

    123
    • Table 53. GPIO[12] truth table

      123
    • Figure 42. GPIO[12] block diagram

      124
  • 22.14 GPIO[13]

    125
    • Table 54. GPIO[13] truth table

      125
    • Figure 43. GPIO[13] block diagram

      126
  • 22.15 GPIO[14]

    127
    • Table 55. GPIO[14] truth table

      127
    • Figure 44. GPIO[14] block diagram

      128
• 23 Serial interface

  129
  • 23.1 Read transaction

    129
    • Figure 45. SPI read transaction

      130
  • 23.2 Write transaction

    130
    • Figure 46. SPI write transaction

      130
    • Figure 47. SPI input timing diagram

      131
    • Figure 48. SPI output timing diagram

      131
• 24 Registers list

  132
  • Table 56. Register address map

    132
• 25 Schematic examples

  135
  • Figure 49. Application with 2 DC motors, 1 stepper motor and 3 power supplies

    135
  • Figure 50. Application with 2 DC motors, a battery charger and 5 power supplies

    136
• 26 Package mechanical data

  137
  • Figure 51. TQFP64 mechanical data an package dimensions

    137
• 27 Revision history

  138
  • Table 57. Document revision history

    138