Инструкции для STMicroelectronics FlexSPIN: SPI configurable stepper and DC multi motor driver evaluation board EVAL6460

Содержание

• Table 1. Device summary

  1
• 1 General description

  10
  • 1.1 Overview

    10
    • Figure 1. Block diagram

      10
  • 1.2 Pin connection

    11
    • Figure 2. Pin connection

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  • 1.3 Pin list

    12
    • Table 2. Pins configuration

      12
• 2 L6460’s main features

  14
• 3 Electrical specifications

  16
  • 3.1 Absolute maximum rating

    16
    • Table 3. Absolute maximum ratings

      16
  • 3.2 Operating ratings specifications

    16
    • Table 4. IC operating ratings

      16
  • 3.3 Electrical characteristics

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    • Table 5. Electrical characteristics

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• 4 Internal supplies

  30
  • 4.1 VSupplyInt regulator

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    • Figure 3. VSupplyInt pin

      30
  • 4.2 Charge pump regulator

    31
    • Figure 4. Charge pump block diagram

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  • 4.3 V3v3 regulator

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• 5 Supervisory system

  32
  • 5.1 Power on reset (POR) circuit

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  • 5.2 nRESET generation circuit

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    • Table 6. Stretch time selection

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    • Figure 5. nReset generation circuit

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  • 5.3 Thermal shut down generation circuit

    35
• 6 Watchdog circuit

  36
  • Figure 6. Watchdog circuit block diagram

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  • Table 7. Watchdog timeout specifications

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• 7 Internal clock oscillator

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• 8 Start-up configurations

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  • Table 8. Possible start-up pins state symbol

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  • 8.1 Operation modes

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    • Table 9. Start-up correspondence

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  • 8.2 Basic device mode

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  • 8.3 Slave device mode

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  • 8.4 Master device mode

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  • 8.5 Single device mode

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  • 8.6 Sub-configurations for slave, master or single device modes

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    • 8.6.1 Bridge mode

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    • 8.6.2 Primary regulator mode (KP)

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    • 8.6.3 Regulators mode

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    • 8.6.4 Simple regulator mode (KT)

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    • 8.6.5 Bridge + VEXT mode

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    • 8.6.6 Secondary regulators mode

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• 9 Power sequencing

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• 10 Power saving modes

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  • 10.1 Standby mode

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    • Figure 7. Standby mode function description

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  • 10.2 Hibernate mode

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  • 10.3 Low power mode

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  • 10.4 nAWAKE pin

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    • Figure 8. nAWAKE function block diagram

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• 11 Linear main regulator

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  • Figure 9. Linear main regulator

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  • Figure 10. Linear main regulator with external bipolar for high current

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• 12 Main switching regulator

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  • 12.1 Pulse skipping operation

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    • Figure 11. Main switching regulator functional blocks

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    • Table 10. Main switching regulator PWM specification

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    • Table 11. Main switching regulator current limit

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• 13 Switching regulator controller

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  • Figure 12. Switching regulator controller functional blocks

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  • 13.1 Pulse skipping operation

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    • Table 12. Switching regulator controller PWM specification

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  • 13.2 Output equivalent circuit

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    • Figure 13. Switching regulator controller output driving: equivalent circuit

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  • 13.3 Switching regulator controller application considerations

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    • Table 13. Switching regulator controller application: feedback reference

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• 14 Power bridges

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  • Figure 14. H Bridge block diagram

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  • Table 14. PWM selection truth table for bridge 1 or 2

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  • Table 15. PWM selection truth table for bridge 3 or 4

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  • Figure 15. Bridge 1 and 2 PWM selection

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  • 14.1 Possible configurations

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    • Table 16. Bridge selection

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    • Table 17. Bridge 3 and 4 configuration

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    • 14.1.1 Full bridge

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      • Table 18. Full bridge truth table

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    • 14.1.2 Parallel configuration (super bridge)

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      • Figure 16. Super bridge configuration

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    • 14.1.3 Half bridge configuration

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      • Figure 17. Half bridge configuration

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      • Table 19. Half bridge truth table

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    • 14.1.4 Switch configuration

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      • Table 20. Switch truth table

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    • 14.1.5 Bipolar stepper configuration

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      • Figure 18. Bipolar stepper configuration

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      • Table 21. Sequencer driver

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      • Table 22. Stepper driving mode

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      • Table 23. Stepper sequencer direction

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      • Table 24. DAC

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      • Table 25. Internal sequencer

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      • Table 26. Stepper off time

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      • Table 27. Stepper fast decay

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    • 14.1.6 Synchronous buck regulator configuration (Bridge 3)

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      • Figure 19. Regulator block diagram

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      • Table 28. PWM specification

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    • 14.1.7 Regulation loop

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      • Figure 20. Internal comparator functional block diagram

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    • 14.1.8 Battery charger or switching regulator (Bridge 4)

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      • Figure 21. Battery charger control loop block diagram

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      • Figure 22. Li-ion battery charge profile

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      • Figure 23. Simple buck regulator

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      • Table 29. Battery charger regulator controller PWM specification

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• 15 AD converter

  80
  • Figure 24. A2D block diagram

    81
  • Table 30. ADC truth table

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  • Table 31. Channel addresses

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  • Table 32. ADC sample times when working as a 8-bit ADC

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  • Table 33. ADC sample time when working as a 9-bit ADC

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  • 15.1 Voltage divider specifications

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    • Table 34. Voltage divider specification

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• 16 Current DAC circuit

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  • Figure 25. Current DAC block diagram

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  • Table 35. Current DAC truth table

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• 17 Operational amplifiers

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  • Figure 26. Configurable 3.3 V operational amplifiers

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• 18 Low voltage power switches

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  • Figure 27. Low power switch block diagram

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• 19 General purpose PWM

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  • 19.1 General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2)

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  • 19.2 Programmable PWM generator (GpPwm)

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• 20 Interrupt controller

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  • Figure 28. Interrupt controller diagram

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  • Table 36. Interrupt controller event

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• 21 Digital comparator

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  • Figure 29. Digital comparator block diagram

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  • Table 37. Comparison type truth table

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  • Table 38. DataX selection truth table

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• 22 GPIO pins

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  • Table 39. GPIO functions description

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  • Table 40. Abbreviations

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  • 22.1 GPIO[0]

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    • Table 41. GPIO[0] truth table

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    • Figure 30. GPIO[0] block diagram

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  • 22.2 GPIO[1]

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    • Table 42. GPIO[1] truth table

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    • Figure 31. GPIO[1] block diagram

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  • 22.3 GPIO[2]

    103
    • Table 43. GPIO[2] truth table

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    • Figure 32. GPIO[2] block diagram

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  • 22.4 GPIO[3]

    105
    • Table 44. GPIO[3] truth table

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    • Figure 33. GPIO[3] block diagram

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  • 22.5 GPIO[4]

    107
    • Table 45. GPIO[4] truth table

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    • Figure 34. GPIO[4] block diagram

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  • 22.6 GPIO[5]

    109
    • Table 46. GPIO[5] truth table

      109
    • Figure 35. GPIO[5] block diagram

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  • 22.7 GPIO[6]

    111
    • Table 47. GPIO[6] truth table

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    • Figure 36. GPIO[6] block diagram

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  • 22.8 GPIO[7]

    113
    • Table 48. GPIO[7] truth table

      113
    • Figure 37. GPIO[7] block diagram

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  • 22.9 GPIO[8]

    115
    • Table 49. GPIO[8] truth table

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    • Figure 38. GPIO[8] block diagram

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  • 22.10 GPIO[9]

    117
    • Table 50. GPIO[9] truth table

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    • Figure 39. GPIO[9] block diagram

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  • 22.11 GPIO[10]

    119
    • Table 51. GPIO[10] truth table

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    • Figure 40. GPIO[10] block diagram

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  • 22.12 GPIO[11]

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    • Table 52. GPIO[11] truth table

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    • Figure 41. GPIO[11] block diagram

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  • 22.13 GPIO[12]

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    • Table 53. GPIO[12] truth table

      123
    • Figure 42. GPIO[12] block diagram

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  • 22.14 GPIO[13]

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    • Table 54. GPIO[13] truth table

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    • Figure 43. GPIO[13] block diagram

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  • 22.15 GPIO[14]

    127
    • Table 55. GPIO[14] truth table

      127
    • Figure 44. GPIO[14] block diagram

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• 23 Serial interface

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  • 23.1 Read transaction

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    • Figure 45. SPI read transaction

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  • 23.2 Write transaction

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    • Figure 46. SPI write transaction

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    • Figure 47. SPI input timing diagram

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    • Figure 48. SPI output timing diagram

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• 24 Registers list

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  • Table 56. Register address map

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• 25 Schematic examples

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  • Figure 49. Application with 2 DC motors, 1 stepper motor and 3 power supplies

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  • Figure 50. Application with 2 DC motors, a battery charger and 5 power supplies

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• 26 Package mechanical data

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  • Figure 51. TQFP64 mechanical data an package dimensions

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• 27 Revision history

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  • Table 57. Document revision history

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