STMicroelectronics L6227 DMOS Evaluation Board EVAL6227PD マニュアル

目次

• 1 Block diagram

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  • Figure 1. Block diagram

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• 2 Maximum ratings

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  • Table 1. Absolute maximum ratings

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  • Table 2. Recommended operating conditions

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  • Table 3. Thermal data

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• 3 Pin connections

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  • Figure 2. Pin connections (top view)

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  • Table 4. Pin description

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• 4 Electrical characteristics

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  • Table 5. Electrical characteristics (Tamb = 25 °C, Vs = 48 V, unless otherwise specified)

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  • Figure 3. Switching characteristic definition

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  • Figure 4. Overcurrent detection timing definition

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• 5 Circuit description

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  • 5.1 Power stages and charge pump

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    • Table 6. Charge pump external components values

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    • Figure 5. Charge pump circuit

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  • 5.2 Logic inputs

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    • Figure 6. Logic inputs internal structure

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    • Figure 7. ENA and ENB pins open collector driving

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    • Figure 8. ENA and ENB pins push-pull driving

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    • Table 7. Truth table

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• 6 PWM current control

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  • Figure 9. PWM current controller simplified schematic

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  • Figure 10. Output current regulation waveforms

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  • Figure 11. tOFF versus COFF and ROFF

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  • Figure 12. Area where tON can vary maintaining the PWM regulation

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• 7 Slow decay mode

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  • Figure 13. Slow decay mode output stage configurations

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  • 7.1 Non-dissipative overcurrent protection

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    • Figure 14. Overcurrent protection simplified schematic

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    • Figure 15. Overcurrent protection waveforms

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    • Figure 16. tDISABLE versus CEN and REN (VDD = 5 V)

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    • Figure 17. tDELAY versus CEN (VDD = 5 V)

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  • 7.2 Thermal protection

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• 8 Application information

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  • Table 8. Component values for typical application

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  • Figure 18. Typical application

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  • 8.1 Output current capability and IC power dissipation

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    • Figure 19. IC power dissipation versus output current with one full bridge ON at a time

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    • Figure 20. IC power dissipation versus output current with two full bridges ON at the same time

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  • 8.2 Thermal management

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    • Figure 21. Mounting the PowerSO package

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    • Figure 22. PowerSO36 junction ambient thermal resistance versus on-board copper area

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    • Figure 23. PowerDIP24 junction ambient thermal resistance versus on-board copper area

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    • Figure 24. SO24 junction ambient thermal resistance versus on-board copper area

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• 9 Package information

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  • Figure 25. PowerSO36 package outline

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  • Table 9. PowerSO36 package mechanical data

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  • Figure 26. PowerDIP24 package outline

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  • Table 10. PowerDIP24 package mechanical data

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  • Figure 27. SO24 package outline

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  • Table 11. SO24 package mechanical data

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• 10 Revision history

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  • Table 12. Document revision history

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