Epson S1D13708 사용자 설명서
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Epson Research and Development
Vancouver Design Center
S1D13708
Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor
X39A-G-016-01
Issue Date: 01/11/25
2 Interfacing to the MC68VZ328
2.1 The MC68VZ328 System Bus
The Motorola MC68VZ328 “Dragonball VZ” is the third generation in the Dragonball
microprocessor family. The Dragonball VZ is an integrated controller designed for
handheld products. It is based upon the FLX68000 microprocessor core and uses a 24-bit
address bus and 16-bit data bus. The Dragonball VZ is faster than its predecessors and the
DRAM controller now supports SDRAM. The bus interface consists of all the standard
MC68000 bus interface signals except AS, plus some new signals intended to simplify the
interface to typical memory and peripheral devices. The 68000 signals are multiplexed with
IrDA, SPI and LCD controller signals.
microprocessor family. The Dragonball VZ is an integrated controller designed for
handheld products. It is based upon the FLX68000 microprocessor core and uses a 24-bit
address bus and 16-bit data bus. The Dragonball VZ is faster than its predecessors and the
DRAM controller now supports SDRAM. The bus interface consists of all the standard
MC68000 bus interface signals except AS, plus some new signals intended to simplify the
interface to typical memory and peripheral devices. The 68000 signals are multiplexed with
IrDA, SPI and LCD controller signals.
The MC68000 bus control signals are well documented in the Motorola user manuals, and
are not be described here. The new signals are as follows.
are not be described here. The new signals are as follows.
• Output Enable (OE) is asserted when a read cycle is in progress. It is intended to connect
to the output enable control signal of a typical static RAM, EPROM, or Flash EPROM
device.
device.
• Upper Write Enable and Lower Write Enable (UWE / LWE) are asserted during
memory write cycles for the upper and lower bytes of the 16-bit data bus. They may be
directly connected to the write enable inputs of a typical memory device.
directly connected to the write enable inputs of a typical memory device.
2.2 Chip-Select Module
The MC68VZ328 can generate up to 8 chip select outputs which are organized into four
groups (A through D).
groups (A through D).
Each chip select group has a common base address register and address mask register
allowing the base address and block size of the entire group to be set. In addition, each chip
select within a group has its own address compare and address mask register to activate the
chip select for a subset of the group’s address block. Each chip select may also be individ-
ually programmed to control an 8 or 16-bit device. Lastly, each chip select can either
generate from 0 through 6 wait states internally, or allow the memory or peripheral device
to terminate the cycle externally using the standard MC68000 DTACK signal.
allowing the base address and block size of the entire group to be set. In addition, each chip
select within a group has its own address compare and address mask register to activate the
chip select for a subset of the group’s address block. Each chip select may also be individ-
ually programmed to control an 8 or 16-bit device. Lastly, each chip select can either
generate from 0 through 6 wait states internally, or allow the memory or peripheral device
to terminate the cycle externally using the standard MC68000 DTACK signal.
Chip select groups A and B are used to control ROM, SRAM, and Flash memory devices
and have a block size of 128K bytes to 16M bytes. Chip select A0 is active immediately
after reset and is a global chip select so it is typically used to control a boot EPROM device.
A0 ceases to decode globally once its chip select registers are programmed. Groups C and
D are special in that they can also control DRAM interfaces. These last two groups have
block size of 32K bytes to 4M bytes.
and have a block size of 128K bytes to 16M bytes. Chip select A0 is active immediately
after reset and is a global chip select so it is typically used to control a boot EPROM device.
A0 ceases to decode globally once its chip select registers are programmed. Groups C and
D are special in that they can also control DRAM interfaces. These last two groups have
block size of 32K bytes to 4M bytes.