사용자 설명서차례S1D13708 TECHNICAL MANUAL1COMPREHENSIVE SUPPORT TOOLS3Documentation3Evaluation/Demonstration Board3Application Engineering Support3Application Engineering Support3S1D13708 Embedded Memory LCD Controller July 20015FEATURES5System Block Diagram5DESCRIPTION6Memory Interface6CPU Interface6Display Support6Power Down Modes6Display Modes6Clock Source6Operating Voltage6Package6Hardware Functional Specification7Table of Contents9List of Tables13List of Figures171 Introduction211.1 Scope211.2 Overview Description212 Features222.1 Integrated Frame Buffer222.2 CPU Interface222.3 Display Support222.4 Display Modes232.5 Display Features232.6 Clock Source232.7 Operating Voltage242.8 Miscellaneous243 Typical System Implementation Diagrams25Figure 31 Typical System Diagram (Generic #1 Bus)25Figure 32 Typical System Diagram (Generic #2 Bus)25Figure 33 Typical System Diagram (Hitachi SH-4 Bus)26Figure 34 Typical System Diagram (Hitachi SH-3 Bus)27Figure 35 Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000)28Figure 36 Typical System Diagram (MC68K #2, Motorola 32-Bit 68030)29Figure 37 Typical System Diagram (Motorola REDCAP2 Bus)30Figure 38 Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus)31Figure 39 Typical System Diagram (Indirect Interface, Mode 68)31Figure 310 Typical System Diagram (Indirect Interface, Mode 80)324 Pins334.1 Pinout Diagram - PFBGA - 120pin33Figure 41 Pinout Diagram - PFBGA 120-pin33Table 41: PFBGA 120-pin Mapping334.2 Pinout Diagram - Die Form34Table 42: S1D13708 Pad Layout344.3 Pin Descriptions354.3.1 Host Interface35Table 43: Host Interface Pin Descriptions354.3.2 LCD Interface40Table 44: LCD Interface Pin Descriptions404.3.3 Clock Input43Table 45: Clock Input Pin Descriptions434.3.4 Miscellaneous43Table 46: Miscellaneous Pin Descriptions434.3.5 Power And Ground43Table 47: Power And Ground Pin Descriptions434.4 Summary of Configuration Options44Table 48: Summary of Power-On/Reset Options444.5 Host Bus Interface Pin Mapping45Table 49: Host Bus Interface Pin Mapping454.6 LCD Interface Pin Mapping46Table 410: LCD Interface Pin Mapping465 D.C. Characteristics47Table 51: Absolute Maximum Ratings (Preliminary - Subject to Change)47Table 52: Recommended Operating Conditions47Table 53: Electrical Characteristics for VDD = 3.3V typical476 A.C. Characteristics486.1 Clock Timing486.1.1 Input Clocks48Figure 61 Clock Input Requirements48Table 61: Clock Input Requirements for CLKI when CLKI to BCLK divide > 148Table 62: Clock Input Requirements for CLKI when CLKI to BCLK divide = 149Table 63: Clock Input Requirements for CLKI2496.1.2 Internal Clocks49Table 64: Internal Clock Requirements496.2 CPU Interface Timing506.2.1 Generic #1 Interface Timing50Figure 62 Generic #1 Interface Timing50Table 65: Generic #1 Interface Timing516.2.2 Generic #2 Interface Timing52Figure 63 Generic #2 Interface Timing52Table 66: Generic #2 Interface Timing536.2.3 Hitachi SH-4 Interface Timing54Figure 64 Hitachi SH-4 Interface Timing54Table 67: Hitachi SH-4 Interface Timing556.2.4 Hitachi SH-3 Interface Timing56Figure 65 Hitachi SH-3 Interface Timing56Table 68: Hitachi SH-3 Interface Timing576.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000)58Figure 66 Motorola MC68K #1 Interface Timing58Table 69: Motorola MC68K #1 Interface Timing596.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030)60Figure 67 Motorola MC68K #2 Interface Timing60Table 610: Motorola MC68K #2 Interface Timing616.2.7 Motorola REDCAP2 Interface Timing62Figure 68 Motorola REDCAP2 Interface Timing62Table 611: Motorola REDCAP2 Interface Timing636.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328)64Figure 69 Motorola DragonBall Interface with DTACK Timing64Table 612: Motorola DragonBall Interface with DTACK Timing656.2.9 Motorola DragonBall Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328)66Figure 610 Motorola DragonBall Interface without DTACK# Timing66Table 613: Motorola DragonBall Interface without DTACK Timing676.2.10 Indirect Interface Timing (Mode 68)68Figure 611 Indirect Interface Timing (Mode 68)68Table 614: Indirect Interface Timing (Mode 68)696.2.11 Indirect Interface Timing (Mode 80)70Figure 612 Indirect Interface Timing (Mode 80)70Table 615: Indirect Interface Timing (Mode 80)716.3 LCD Power Sequencing726.3.1 Passive/TFT Power-On Sequence72Figure 613 Passive/TFT Power-On Sequence Timing72Table 616: Passive/TFT Power-On Sequence Timing726.3.2 Passive/TFT Power-Off Sequence73Figure 614 Passive/TFT Power-Off Sequence Timing73Table 617: Passive/TFT Power-Off Sequence Timing736.4 Display Interface74Figure 615 Panel Timing Parameters74Table 618: Panel Timing Parameter Definition and Register Summary756.4.1 Generic STN Panel Timing76Figure 616 Generic STN Panel Timing766.4.2 Single Monochrome 4-Bit Panel Timing78Figure 617 Single Monochrome 4-Bit Panel Timing78Figure 618 Single Monochrome 4-Bit Panel A.C. Timing79Table 619: Single Monochrome 4-Bit Panel A.C. Timing796.4.3 Single Monochrome 8-Bit Panel Timing80Figure 619 Single Monochrome 8-Bit Panel Timing80Figure 620 Single Monochrome 8-Bit Panel A.C. Timing81Table 620: Single Monochrome 8-Bit Panel A.C. Timing816.4.4 Single Color 4-Bit Panel Timing82Figure 621 Single Color 4-Bit Panel Timing82Figure 622 Single Color 4-Bit Panel A.C. Timing83Table 621: Single Color 4-Bit Panel A.C. Timing836.4.5 Single Color 8-Bit Panel Timing (Format 1)84Figure 623 Single Color 8-Bit Panel Timing (Format 1)84Figure 624 Single Color 8-Bit Panel A.C. Timing (Format 1)85Table 622: Single Color 8-Bit Panel A.C. Timing (Format 1)856.4.6 Single Color 8-Bit Panel Timing (Format 2)86Figure 625 Single Color 8-Bit Panel Timing (Format 2)86Figure 626 Single Color 8-Bit Panel A.C. Timing (Format 2)87Table 623: Single Color 8-Bit Panel A.C. Timing (Format 2)876.4.7 Single Color 16-Bit Panel Timing88Figure 627 Single Color 16-Bit Panel Timing88Figure 628 Single Color 16-Bit Panel A.C. Timing89Table 624: Single Color 16-Bit Panel A.C. Timing896.4.8 Generic TFT Panel Timing90Figure 629 Generic TFT Panel Timing906.4.9 9/12/18-Bit TFT Panel Timing91Figure 630 18-Bit TFT Panel Timing91Figure 631 TFT A.C. Timing92Table 625: TFT A.C. Timing936.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx)94Figure 632 160x160 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing94Table 626: 160x160 Sharp ‘Direct’ HR-TFT Horizontal Timing95Figure 633 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing96Table 627: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing976.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01)98Figure 634 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing98Table 628: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing99Figure 635 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing99Table 629: 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing996.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR)100Figure 636 160x240 Epson D-TFD Panel Horizontal Timing100Table 630: 160x240 Epson D-TFD Panel Horizontal Timing101Figure 637 160x240 Epson D-TFD Panel GCP Horizontal Timing102Table 631: 160x240 Epson D-TFD Panel GCP Horizontal Timing102Figure 638 160x240 Epson D-TFD Panel Vertical Timing103Table 632: 160x240 Epson D-TFD Panel Vertical Timing1036.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR)104Figure 639 320x240 Epson D-TFD Panel Horizontal Timing104Table 633: 320x240 Epson D-TFD Panel Horizontal Timing105Figure 640 320x240 Epson D-TFD Panel GCP Horizontal Timing106Table 634: 320x240 Epson D-TFD Panel GCP Horizontal Timing106Figure 641 320x240 Epson D-TFD Panel Vertical Timing107Table 635: 320x240 Epson D-TFD Panel Vertical Timing1076.4.14 TFT Type 2 Panel Timing108Figure 642 TFT Type 2 Horizontal Timing108Table 636: TFT Type 2 Horizontal Timing109Figure 643 TFT Type 2 Vertical Timing110Table 637: TFT Type 2 Vertical Timing1106.4.15 TFT Type 3 Panel Timing111Figure 644 TFT Type 3 Horizontal Timing111Table 638: TFT Type 3 Horizontal Timing112Figure 645 TFT Type 3 Vertical Timing113Table 639: TFT Type 3 Vertical Timing1146.4.16 TFT Type 4 Panel Timing115Figure 646 TFT Type 4 Panel Timing115Figure 647 TFT Type 4 A.C. Timing116Table 640: TFT Type 4 A.C. Timing1177 Clocks1187.1 Clock Descriptions1187.1.1 BCLK118Table 71: BCLK Clock Selection1187.1.2 MCLK118Table 72: MCLK Clock Selection1197.1.3 PCLK119Table 73: PCLK Clock Selection 119Table 74: Relationship between MCLK and PCLK1217.1.4 PWMCLK121Table 75: PWMCLK Clock Selection1217.2 Clock Selection122Figure 71 Clock Selection1227.3 Clocks versus Functions123Table 76: S1D13708 Internal Clock Requirements1238 Registers1248.1 Register Mapping1248.2 Register Set125Table 81: S1D13708 Register Set1258.3 Register Descriptions1278.3.1 Read-Only Configuration Registers1278.3.2 Clock Configuration Registers128Table 82: MCLK Divide Selection128Table 83: PCLK Divide Selection128Table 84: PCLK Source Selection1298.3.3 Look-Up Table Registers1298.3.4 Panel Configuration Registers132Table 85: Panel Data Width Selection132Table 86: HRTFT/D-TFD Panel Resolution Selection132Table 87: LCD Panel Type Selection1338.3.5 Display Mode Registers139Table 88: Inverse Video Mode Select Options140Table 89: LCD Bit-per-pixel Selection141Figure 81 Display Data Byte/Word Swap142Table 810: SwivelViewTM Mode Select Options1428.3.6 Picture-in-Picture Plus Registers144Table 811: 32-bit Address Increments for Color Depth145Table 812: 32-bit Address Increments for Color Depth146Table 813: 32-bit Address Increments for Color Depth147Table 814: 32-bit Address Increments for Color Depth1488.3.7 Miscellaneous Registers1498.3.8 General IO Pins Registers1518.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers156Figure 82 PWM Clock/CV Pulse Block Diagram156Table 815: PWM Clock Control156Table 816: CV Pulse Control157Table 817: PWM Clock Divide Select Options158Table 818: CV Pulse Divide Select Options158Table 819: PWMOUT Duty Cycle Select Options1598.3.10 Extended Registers160Table 820: Extended Panel Type Selection161Table 821: VCLK Hold165Table 822: VCLK Setup165Table 823: AP Pulse Width166Table 824: AP Rising Position166Table 825: GPO2 PCLK2 Divide Rate170Table 826: GPO1 PCLK1 Divide Rate170Table 827: Number of Source Driver ICs1769 Frame Rate Calculation17710 Display Data Formats178Figure 101 4/8/16 Bit-Per-Pixel Display Data Memory Organization17811 Look-Up Table Architecture17911.1 Monochrome Modes1791 Bit-per-pixel Monochrome Mode179Figure 111 1 Bit-per-pixel Monochrome Mode Data Output Path1792 Bit-per-pixel Monochrome Mode179Figure 112 2 Bit-per-pixel Monochrome Mode Data Output Path1794 Bit-per-pixel Monochrome Mode180Figure 113 4 Bit-per-pixel Monochrome Mode Data Output Path1808 Bit-per-pixel Monochrome Mode180Figure 114 8 Bit-per-pixel Monochrome Mode Data Output Path18016 Bit-Per-Pixel Monochrome Mode18111.2 Color Modes1811 Bit-Per-Pixel Color181Figure 115 1 Bit-Per-Pixel Color Mode Data Output Path1812 Bit-Per-Pixel Color182Figure 116 2 Bit-Per-Pixel Color Mode Data Output Path1824 Bit-Per-Pixel Color183Figure 117 4 Bit-Per-Pixel Color Mode Data Output Path1838 Bit-per-pixel Color Mode184Figure 118 8 Bit-per-pixel Color Mode Data Output Path18416 Bit-Per-Pixel Color Mode18412 SwivelView™18512.1 Concept18512.2 90 SwivelView™185Figure 121 Relationship Between The Screen Image and the Image Refreshed in 90° SwivelView.18512.2.1 Register Programming18612.3 180 SwivelView™187Figure 122 Relationship Between The Screen Image and the Image Refreshed in 180° SwivelView.18712.3.1 Register Programming18712.4 270 SwivelView™188Figure 123 Relationship Between The Screen Image and the Image Refreshed in 270° SwivelView.18812.4.1 Register Programming18913 Picture-in-Picture Plus (PIP+)19013.1 Concept190Figure 131 Picture-in-Picture Plus with SwivelView disabled19013.2 With SwivelView Enabled19113.2.1 SwivelView 90191Figure 132 Picture-in-Picture Plus with SwivelView 90 enabled19113.2.2 SwivelView 180191Figure 133 Picture-in-Picture Plus with SwivelView 180 enabled19113.2.3 SwivelView 270192Figure 134 Picture-in-Picture Plus with SwivelView 270 enabled19214 Ink Layer19314.1 Memory Mapping193Figure 141 Memory Mapping for Ink Layer19314.2 Controlling the Ink Layer193Figure 142 Transparent Color Example19414.3 Limitations19415 Indirect Interface19515.1 Mode 68196Figure 151 Sample timing of “register write” with Mode 68196Figure 152 Sample timing of “register read” with Mode 68197Figure 153 Sample timing of “memory write” with Mode 68, Big Endian198Figure 154 Sample timing of “memory read” with Mode 68, Big Endian200Figure 155 Sample timing of “register write” for Mode 68 when Memory Access Select Enabled202Figure 156 Sample timing of “register read” for Mode 68 when Memory Access Select Enabled20415.2 Mode 80206Figure 157 Sample timing of “register write” with Mode 80206Figure 158 Sample timing of “register read” with Mode 80208Figure 159 Sample timing of “memory write” with mode 80, little endian209Figure 1510 Sample timing of “memory read” with mode 80, Little endian211Figure 1511 Sample timing of “memory write” for Mode 80 when Memory Access Select Enabled213Figure 1512 Sample timing of “memory read” for Mode 80 when Memory Access Select Enabled21515.3 Limitations21616 Embedded Crystal Oscillator21716.1 Oscillator Circuit217Figure 161 Recommended Crystal Oscillator Circuit21717 Big-Endian Bus Interface21817.1 Byte Swapping Bus Data21817.1.1 16 Bpp Color Depth219Figure 171 Byte-swapping for 16 Bpp21917.1.2 1/2/4/8 Bpp Color Depth220Figure 172 Byte-swapping for 1/2/4/8 Bpp22018 Power Save Mode221Table 181: Power Save Mode Function Summary22119 Mechanical Data222Figure 191 Mechanical Data PFBGA 120-pin Package22220 References22321 Technical Support224S1D13708 Embedded Memory LCD Controller225Table of Contents227List of Tables229List of Figures2311 Introduction2332 Identifying the S1D137082343 Initialization2354 Memory Models2364.1 Memory Organization for One Bit-per-pixel (2 Colors/Gray Shades)236Figure 41: Pixel Storage for 1 Bpp in One Byte of Display Buffer2364.2 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades)236Figure 42: Pixel Storage for 2 Bpp in One Byte of Display Buffer2364.3 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades)237Figure 43: Pixel Storage for 4 Bpp in One Byte of Display Buffer2374.4 Memory Organization for 8 Bpp (256 Colors/64 Gray Shades)237Figure 44: Pixel Storage for 8 Bpp in One Byte of Display Buffer2374.5 Memory Organization for 16 Bpp (65536 Colors/64 Gray Shades)238Figure 45: Pixel Storage for 16 Bpp in Two Bytes of Display Buffer2385 Look-Up Table (LUT)2395.1 Registers2395.1.1 Look-Up Table Registers2395.2 Look-Up Table Organization242Table 51: Look-Up Table Configurations2425.2.1 Gray Shade Modes243Table 52: Suggested LUT Values for 1 Bpp Gray Shade243Table 53: Suggested LUT Values for 4 Bpp Gray Shade243Table 54: Suggested LUT Values for 4 Bpp Gray Shade244Table 55: Suggested LUT Values for 8 Bpp Gray Shade2455.2.2 Color Modes247Table 56: Suggested LUT Values for 1 bpp Color247Table 57: Suggested LUT Values for 2 bpp Color247Table 58: Suggested LUT Values for 4 bpp Color248Table 59: Suggested LUT Values for 8 bpp Color2496 Power Save Mode2516.1 Overview2516.2 Registers2526.2.1 Power Save Mode Enable2526.2.2 Memory Controller Power Save Status2526.3 LCD Power Sequencing2536.4 Enabling Power Save Mode2546.5 Disabling Power Save Mode2547 SwivelView‘2557.1 SwivelView Registers255Table 71: SwivelViewTM Mode Select Options2557.2 Examples2577.3 Limitations2617.3.1 SwivelView 0 and 1802617.3.2 SwivelView 90 and 2702618 Picture-In-Picture Plus2628.1 Concept262Figure 81: Picture-in-Picture Plus with SwivelView disabled2628.2 Registers262Table 81: 32-bit Address Increments for Color Depth265Table 82: 32-bit Address Increments for Color Depth267Table 83: 32-bit Address Increments for Color Depth269Table 84: 32-bit Address Increments for Color Depth2708.3 Picture-In-Picture-Plus Examples2728.3.1 SwivelView 0 (Landscape Mode)272Figure 82: Picture-in-Picture Plus with SwivelView disabled2728.3.2 SwivelView 90275Figure 83: Picture-in-Picture Plus with SwivelView 90 enabled2758.3.3 SwivelView 180278Figure 84: Picture-in-Picture Plus with SwivelView 180 enabled2788.3.4 SwivelView 270282Figure 85: Picture-in-Picture Plus with SwivelView 270 enabled2828.4 Limitations2868.4.1 SwivelView 0 and 1802868.4.2 SwivelView 90 and 2702869 Hardware Abstraction Layer2879.1 Introduction2879.2 API for the HAL Library287Table 91: HAL Library API2879.2.1 Startup Routines2889.2.2 Memory Access2909.2.3 Register Access2919.2.4 Clock Support2939.2.5 Miscellaneous29410 Sample Code29611 Sales and Technical Support297S1D13708 Register Summary X39A-R-001-0129913708CFG Configuration Program303Table of Contents30513708CFG307S1D13708 Supported Evaluation Platforms307Installation307Usage30713708CFG Configuration Tabs308General Tab308Preferences Tab310Clocks Tab311Panel Tab316Panel Power Tab320Registers Tab32113708CFG Menus322Open...322Save323Save As...323Configure Multiple323Export325Enable Tooltips326ERD on the Web326About 13708CFG326Comments32613708PLAY Diagnostic Utility32713708PLAY329S1D13708 Supported Evaluation Platforms329Installation330Usage330Commands33113708PLAY Example337Script Files33813708BMP Demonstration Program33913708BMP341S1D13708 Supported Evaluation Platforms341Installation341Usage34213708BMP Examples342Comments342Wind River WindML v2.0 Display Drivers343Wind River WindML v2.0 DISPLAY DRIVERS345Building a WindML v2.0 Display Driver3461. Create a working directory and unzip the WindML display driver into it.3462. Configure for the target execution model.3463. Build a boot ROM image.3464. Create a bootable disk (in drive A:).3465. If necessary, generate a new mode0.h configuration file.3466. Build the WindML v2.0 library.3477. Open the S1D13708 workspace.3478. Add support for single line comments.347a. In the Tornado “Workspace Views” window, click on the “Builds” tab.347b. Expand the “8bpp Builds” (or “16bpp Builds”) view by clicking on the “+” next to it. The expan...347c. Select the “C/C++ compiler” tab to display the command switches used in the build. Remove the ...3479. Compile the VxWorks image.34710. Copy the VxWorks file to the diskette.34711. Start the VxWorks demo.347Linux Console Driver349Linux Console Driver351Building the Console Driver for Linux Kernel 2.2.x3521. Acquire the Linux kernel source code.3522. Unzip the console driver files.3523. Copy the console driver files to the build directory.3524. Modify s1d13708.h3535. Configure the video options.3536. Compile and install the kernel.3537. Boot to the Linux operating system.354Building the Console Driver for Linux Kernel 2.4.x3551. Acquire the Linux kernel source code.3552. Unzip the console driver files.3553. Copy the console driver files to the build directory. Make the directory /usr/src/linux/driver...3554. Modify s1d13708.h3565. Configure the video options.3566. Compile and install the kernel3577. Boot to the Linux operating system357QNX Photon v2.0 Display Driver359QNX Photon v2.0 Display Driver361Building the Photon v2.0 Display Driver362Unpack the Graphics Driver Development Kit Archive362Configure the Driver362Build the Driver362Installing the Driver363Run the Driver363Comments364Windows® CE 3.x Display Drivers365WINDOWS® CE 3.0 DISPLAY DRIVER367Example Driver Builds368Installation for CEPC Environment372Configuration373Compile Switches373Mode File374Resource Management Issues375Comments378Power Consumption3791 S1D13708 Power Consumption3811.1 Conditions382Table 11: S1D13708 Power Consumption3822 Summary383Interfacing to the NEC VR4102 / VR4111 Microprocessors385Table of Contents387List of Tables389List of Figures3891 Introduction3912 Interfacing to the NEC VR4102/VR41113922.1 The NEC VR41XX System Bus3922.1.1 Overview3922.1.2 LCD Memory Access Cycles393Figure 21: NEC VR4102/VR4111 Read/Write Cycles3933 S1D13708 Host Bus Interface3943.1 Host Bus Interface Pin Mapping394Table 31: Host Bus Interface Pin Mapping3943.2 Host Bus Interface Signals3954 VR4102/VR4111 to S1D13708 Interface3964.1 Hardware Description396Figure 41: Typical Implementation of VR4102/VR4111 to S1D13708 Interface3964.2 S1D13708 Hardware Configuration397Table 41: Summary of Power-On/Reset Configuration Options397Table 42: CLKI to BCLK Divide Selection3974.3 NEC VR4102/VR4111 Configuration3985 Software3996 References4006.1 Documents4006.2 Document Sources4007 Technical Support4017.1 Epson LCD Controllers (S1D13708)4017.2 NEC Electronics Inc.401Interfacing to the NEC VR4181A™ Microprocessor403Table of Contents405List of Tables407List of Figures4071 Introduction4092 Interfacing to the NEC VR4181A4102.1 The NEC VR4181A System Bus4102.1.1 Overview4102.1.2 LCD Memory Access Signals4113 S1D13708 Host Bus Interface4123.1 Host Bus Interface Pin Mapping412Table 31: Host Bus Interface Pin Mapping4123.2 Host Bus Interface Signals4134 VR4181A to S1D13708 Interface4144.1 Hardware Description414Figure 41: Typical Implementation of VR4181A to S1D13708 Interface4144.2 S1D13708 Hardware Configuration415Table 41: Summary of Power-On/Reset Configuration Options415Table 42: CLKI to BCLK Divide Selection4154.3 NEC VR4181A Configuration4165 Software4176 References4186.1 Documents4186.2 Document Sources4187 Technical Support4197.1 Epson LCD Controllers (S1D13708)4197.2 NEC Electronics Inc.419Interfacing to the Motorola MPC821 Microprocessor421Document Number: X39A-G-009-01421Table of Contents423List of Tables425List of Figures4251 Introduction4272 Interfacing to the MPC8214282.1 The MPC8XX System Bus4282.2 MPC8XX Bus Overview4282.2.1 Normal (Non-Burst) Bus Transactions429Figure 21: Power PC Memory Read Cycle429Figure 22: Power PC Memory Write Cycle4302.2.2 Burst Cycles4302.3 Memory Controller Module4312.3.1 General-Purpose Chip Select Module (GPCM)431Figure 23: GPCM Memory Devices Timing4322.3.2 User-Programmable Machine (UPM)4323 S1D13708 Host Bus Interface4333.1 Host Bus Interface Pin Mapping433Table 31: Host Bus Interface Pin Mapping4333.2 Host Bus Interface Signals4344 MPC821 to S1D13708 Interface4354.1 Hardware Description435Figure 41: Typical Implementation of MPC821 to S1D13708 Interface4354.2 MPC821ADS Evaluation Board Hardware Connections436Table 41: List of Connections from MPC821ADS to S1D13708 4364.3 S1D13708 Hardware Configuration438Table 42: Summary of Power-On/Reset Configuration Options438Table 43: CLKI to BCLK Divide Selection4384.4 Register/Memory Mapping4384.5 MPC821 Chip Select Configuration4394.6 Test Software4405 Software4416 References4426.1 Documents4426.2 Document Sources4427 Technical Support4437.1 EPSON LCD/CRT Controllers (S1D13708)4437.2 Motorola MPC821 Processor443Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor445Table of Contents447List of Tables449List of Figures4491 Introduction4512 Interfacing to the MCF53074522.1 The MCF5307 System Bus4522.1.1 Overview4522.1.2 Normal (Non-Burst) Bus Transactions452Figure 21: MCF5307 Memory Read Cycle453Figure 22: MCF5307 Memory Write Cycle4532.1.3 Burst Cycles4532.2 Chip-Select Module454Figure 23: Chip Select Module Outputs Timing4543 S1D13708 Host Bus Interface4553.1 Host Bus Interface Pin Mapping455Table 31: Host Bus Interface Pin Mapping4553.2 Host Bus Interface Signals4564 MCF5307 To S1D13708 Interface4574.1 Hardware Description457Figure 41: Typical Implementation of MCF5307 to S1D13708 Interface4574.2 S1D13708 Hardware Configuration458Table 41: Summary of Power-On/Reset Configuration Options458Table 42: CLKI to BCLK Divide Selection4584.3 Register/Memory Mapping4594.4 MCF5307 Chip Select Configuration4595 Software4606 References4616.1 Documents4616.2 Document Sources4617 Technical Support4627.1 EPSON LCD Controllers (S1D13708)4627.2 Motorola MCF5307 Processor462Connecting to the Sharp HR-TFT Panels463Table of Contents465List of Tables467List of Figures4671 Introduction4692 Connecting to the Sharp LQ039Q2DS01 HR-TFT4702.1 External Power Supplies4702.1.1 Gray Scale Voltages for Gamma Correction470Figure 21: Sharp LQ039Q2DS01 Gray Scale Voltage (V0-V9) Generation4702.1.2 Digital/Analog Power Supplies4712.1.3 DC Gate Driver Power Supplies471Figure 22: Panel Gate Driver DC Power Supplies4712.1.4 AC Gate Driver Power Supplies472Figure 23: Panel Gate Driver AC Power Supplies4722.2 HR-TFT MOD Signal473Figure 24: HR-TFT Power-On/Off Sequence Timing473Table 21: HR-TFT Power-On/Off Sequence Timing4732.3 S1D13708 to LQ039Q2DS01 Pin Mapping474Table 22: S1D13708 to LQ039Q2DS01 Pin Mapping4743 Connecting to the Sharp LQ031B1DDxx HR-TFT4763.1 External Power Supplies4763.1.1 Gray Scale Voltages for Gamma Correction476Figure 31: Sharp LQ031B1DDxx Gray Scale Voltage (V0-V9) Generation4763.1.2 Digital/Analog Power Supplies4773.1.3 DC Gate Driver Power Supplies4773.1.4 AC Gate Driver Power Supplies4773.2 HR-TFT MOD Signal4773.3 S1D13708 to LQ031B1DDxx Pin Mapping478Table 31: S1D13708 to LQ031B1DDxx Pin Mapping4784 Test Software4805 References4815.1 Documents4815.2 Document Sources4816 Technical Support4826.1 EPSON LCD Controllers (S1D13708)4826.2 Sharp HR-TFT Panel482Interfacing to the Motorola RedCap2483Table of Contents485List of Tables487List of Figures4871 Introduction4892 Interfacing to the REDCAP24902.1 The REDCAP2 System Bus4902.2 Overview4902.3 Bus Transactions490Figure 21: REDCAP2 Memory Read Cycle491Figure 22: REDCAP2 Memory Write Cycle4913 S1D13708 Host Bus Interface4923.1 Host Bus Interface Pin Mapping492Table 31: Host Bus Interface Pin Mapping4923.2 Host Bus Interface Signals4934 REDCAP2 to S1D13708 Interface4944.1 Hardware Description494Figure 41: Typical Implementation of REDCAP2 to S1D13708 Interface4944.2 Hardware Connections495Table 41: List of Connections for REDCAP2 ADM4954.3 S1D13708 Hardware Configuration497Table 42: Summary of Power-On/Reset Options4974.4 Register/Memory Mapping4974.5 REDCAP2 Chip Select Configuration4985 Software4996 References5006.1 Documents5006.2 Document Sources5007 Technical Support5017.1 EPSON LCD/CRT Controllers (S1D13708)5017.2 Motorola REDCAP2 Processor501Interfacing to 8-bit Processors503Table of Contents505List of Tables507List of Figures5071 Introduction5092 Interfacing to an 8-bit Processor5102.1 The Generic 8-bit Processor System Bus5103 S1D13708 Host Bus Interface5113.1 Host Bus Interface Pin Mapping511Table 31: Host Bus Interface Pin Mapping5113.2 Host Bus Interface Signals5124 8-Bit Processor to S1D13708 Interface5134.1 Hardware Connections513Figure 41: Typical Implementation of 8-bit Processor to S1D13708 Interface5134.2 S1D13708 Hardware Configuration514Table 41: Summary of Power-On/Reset Configuration Options514Table 42: CLKI to BCLK Divide Selection5144.3 Register/Memory Mapping5145 Software5156 References5166.1 Documents5166.2 Document Sources5167 Technical Support5177.1 EPSON LCD Controllers (S1D13708)517Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor519Document Number: X39A-G-016-01519Table of Contents521List of Tables523List of Figures5231 Introduction5252 Interfacing to the MC68VZ3285262.1 The MC68VZ328 System Bus5262.2 Chip-Select Module5263 S1D13708 Host Bus Interface5273.1 Host Bus Interface Pin Mapping527Table 31: Host Bus Interface Pin Mapping5273.2 Host Bus Interface Signals5284 MC68VZ328 to S1D13708 Interface5294.1 Hardware Description529Figure 41: Typical Implementation of MC68VZ328 to S1D13708 Interface5294.2 S1D13708 Hardware Configuration530Table 41: Summary of Power-On/Reset Configuration Options530Table 42: CLKI to BCLK Divide Selection5304.2.1 Register/Memory Mapping5314.2.2 MC68VZ328 Chip Select and Pin Configuration531Table 43: WS Bit Programming5315 Software5326 References5336.1 Documents5336.2 Document Sources5337 Technical Support5347.1 EPSON LCD/CRT Controllers (S1D13708)5347.2 Motorola MC68VZ328 Processor534Interfacing to the Intel StrongARM SA-1110 Microprocessor535Document Number: X39A-G-019-01535Table of Contents537List of Tables539List of Figures5391 Introduction5412 Interfacing to the StrongARM SA-1110 Bus5422.1 The StrongARM SA-1110 System Bus5422.1.1 StrongARM SA-1110 Overview5422.1.2 Variable-Latency IO Access Overview5422.1.3 Variable-Latency IO Access Cycles543Figure 21: SA-1110 Variable-Latency IO Read Cycle543Figure 22: SA-1110 Variable-Latency IO Write Cycle5443 S1D13708 Host Bus Interface5453.1 Host Bus Interface Pin Mapping545Table 31: Host Bus Interface Pin Mapping5453.2 Host Bus Interface Signal Descriptions5464 StrongARM SA-1110 to S1D13708 Interface5474.1 Hardware Description547Figure 41: Typical Implementation of SA-1110 to S1D13708 Interface5474.2 S1D13708 Hardware Configuration548Table 41: Summary of Power-On/Reset Configuration Options548Table 42: CLKI to BCLK Divide Selection5484.3 StrongARM SA-1110 Register Configuration549Table 43: RDFx Parameter Value versus CPU Maximum Frequency5494.4 Register/Memory Mapping5505 Software5516 References5526.1 Documents5526.2 Document Sources5527 Technical Support5537.1 EPSON LCD Controllers (S1D13708)5537.2 Intel StrongARM SA-1110 Processor553Connecting to a Micro-Controller via the Indirect Interface555Table of Contents557List of Tables559List of Figures5591 Introduction5612 Interfacing to a Micro-Controller5622.1 The Indirect Interface5623 S1D13708 Host Bus Interface5633.1 Indirect Mode Bus Interface Pin Mapping563Table 31: Mode 68 8-Bit Data Host Bus Interface Pin Mapping563Table 32: Mode 68 16-Bit Data Host Bus Interface Pin Mapping564Table 33: Mode 80 8-Bit Data Host Bus Interface Pin Mapping564Table 34: Mode 80 16-Bit Data Host Bus Interface Pin Mapping5653.2 Host Bus Interface Signals5664 Micro-Controller to S1D13708 Interface5674.1 Hardware Connections567Figure 41: Typical Implementation of Micro-Controller to S1D13708 Interface5674.2 S1D13708 Hardware Configuration568Table 41: Summary of Power-On/Reset Configuration Options568Table 42: CLKI to BCLK Divide Selection5684.3 Register/Memory Mapping5695 Software5706 References5726.1 Documents5726.2 Document Sources5727 Technical Support5737.1 EPSON LCD Controllers (S1D13708)573크기: 4.61메가바이트페이지: 574Language: English매뉴얼 열기