Emerson PMPPC7448 사용자 설명서

 CPU Interface

PmPPC7448 User’s Manual

CPU interface features include:

• 32-bit address and 64-bit data buses

• Support for Symmetrical Multi-Processing (SMP) in both 60x and MPX bus modes

• Support for up to four slave devices on the same 60x bus

• 166 MHz CPU bus frequency

• CPU address remapping to the PCI

• Support for access, write, and caching protection to a configurable address range

• Support for up to 16 pipelined address transactions

The PmPPC7448 monitor configures the MV64460 controller so that it provides these 32-
bit registers to the PowerPC processor in the correct byte order (assuming the access width 
is 32 bits). The CPU setting of the CPU Configuration register affects the MV64460 behavior 
on subsequent CPU accesses. This register activates with transactions pipeline disabled. In 
order to gain the maximum CPU interface performance, change this default by following 
these steps:

1

Read the CPU Configuration register. This guarantees that all previous transactions in the 
CPU interface pipe are flushed.

2

Program the register to its new value.

3

Read polling of the register until the new data is being read.

Caution:

Setting the CPU Configuration register must be done only once. For example, if the CPU 
interface is configured to support Out of Order (OOO) read completion, changing the 
register to not support OOO read completion is fatal.

The DDR SDRAM controller supports up to four DRAM banks. It has a 16-bit address bus 
(M_DA[13:0] and M_BA[1:0]) and a 72-bit data bus (M_DQ[63:0] and M_CB7[7:0]). The 
DRAM controller supports two DDR DRAM DIMMs—registered and unbuffered. Other fea-
tures include:

• 64-bit wide (+ 8-bit ECC) SDRAM interface