Emerson PMPPC7448 사용자 설명서
System Controller:
Internal (IDMA) Controller
5-4
Device Control Registers
Each bank has its own parameters register and can be programmed to 8, 16, or 32-bits
wide. The device interface consists of 128 bytes of write buffer and 128 bytes of read
buffer.
wide. The device interface consists of 128 bytes of write buffer and 128 bytes of read
buffer.
INTERNAL (IDMA) CONTROLLER
Each of the four DMA engines can move data between any source and any destination, such
as the SDRAM, device, PCI_0, or CPU bus. These engines optimize system performance by
moving large amounts of data without significant CPU intervention. Read and write are
handled independently and concurrently.
as the SDRAM, device, PCI_0, or CPU bus. These engines optimize system performance by
moving large amounts of data without significant CPU intervention. Read and write are
handled independently and concurrently.
Timer/Counter
Each of the four 32-bit wide timer/counters can be selected to operate as a timer or a
counter. Each timer/counter increments with every TCLK rising edge. In counter mode, the
counter counts down to terminal count, stops, and issues an interrupt. In timer mode, the
timer counts down, issues an interrupt on terminal count, reloads itself to the programmed
value, and continues to count. Reads from the counter or timer are completed directly from
the counter, and writes are to the timer/counter register.
counter. Each timer/counter increments with every TCLK rising edge. In counter mode, the
counter counts down to terminal count, stops, and issues an interrupt. In timer mode, the
timer counts down, issues an interrupt on terminal count, reloads itself to the programmed
value, and continues to count. Reads from the counter or timer are completed directly from
the counter, and writes are to the timer/counter register.
PCI INTERFACE
The Emerson PmPPC7448 module complies with the PCI mezzanine card (PMC) form factor
for peripheral component interconnect (PCI) modules and the specification for Processor
PCI Mezzanine Cards (PPMC). The MV64460 supports two 64-bit PCI interfaces, compliant
to the PCI Local Bus Specification revision 2.3. Only PCI0 is functional on the PmPPC7448.
Other features include:
for peripheral component interconnect (PCI) modules and the specification for Processor
PCI Mezzanine Cards (PPMC). The MV64460 supports two 64-bit PCI interfaces, compliant
to the PCI Local Bus Specification revision 2.3. Only PCI0 is functional on the PmPPC7448.
Other features include:
• Support for PCI-to-PCI memory, I/O, and configuration transactions between the two
PCI interfaces
• Support for PCI-to-PCI-X bridging between the two PCI interfaces
• PCI bus speed up to 66 MHz in conventional PCI mode or up to 133 MHz in PCI-X mode
• When both PCI interfaces are functional, they operate in asynchronous clocks to each
other and to the MV64460 core clock
• 32/64-bit PCI master and target operations