Texas Instruments TMS320DM646x 사용자 설명서
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5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
Ethernet Media Access Controller (EMAC) Registers
The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in
and
described in
Figure 53. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
RX7PEND
RX6PEND
RX5PEND
RX4PEND
RX3PEND
RX2PEND
RX1PEND
RX0PEND
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 52. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7
RX7PEND
0-1
RX7PEND raw interrupt read (before mask)
6
RX6PEND
0-1
RX6PEND raw interrupt read (before mask)
5
RX5PEND
0-1
RX5PEND raw interrupt read (before mask)
4
RX4PEND
0-1
RX4PEND raw interrupt read (before mask)
3
RX3PEND
0-1
RX3PEND raw interrupt read (before mask)
2
RX2PEND
0-1
RX2PEND raw interrupt read (before mask)
1
RX1PEND
0-1
RX1PEND raw interrupt read (before mask)
0
RX0PEND
0-1
RX0PEND raw interrupt read (before mask)
96
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
SPRUEQ6 – December 2007