Texas Instruments TMS320DM646x 사용자 설명서
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5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)
Ethernet Media Access Controller (EMAC) Registers
The receive interrupt mask set register (RXINTMASKSET) is shown in
and described in
Figure 55. Receive Interrupt Mask Set Register (RXINTMASKSET)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
RX7MASK
RX6MASK
RX5MASK
RX4MASK
RX3MASK
RX2MASK
RX1MASK
RX0MASK
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset
Table 54. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7
RX7MASK
0-1
Receive channel 7 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
6
RX6MASK
0-1
Receive channel 6 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
5
RX5MASK
0-1
Receive channel 5 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
4
RX4MASK
0-1
Receive channel 4 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
3
RX3MASK
0-1
Receive channel 3 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
2
RX2MASK
0-1
Receive channel 2 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
1
RX1MASK
0-1
Receive channel 1 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
0
RX0MASK
0-1
Receive channel 0 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
98
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
SPRUEQ6 – December 2007