Fujitsu FR81 사용자 설명서
CM71-00105-1E
FUJITSU MICROELECTRONICS LIMITED
129
FR81 Family
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.13
7.13
ANDH (And Halfword Data of Source Register to Data in
Memory)
Memory)
Takes the logical AND of the half-word data at Ri location of the memory and the half-
word data in Rj and stores the results at Ri location of the memory.
word data in Rj and stores the results at Ri location of the memory.
●
Assembler Format
ANDH Rj,@Ri
●
Operation
(Ri) & Rj
→ (Ri)
●
Flag Change
N: Set when the MSB of the operation result is "1", cleared when the MSB (bit15) is "0".
Z: Set when the operation result is zero, cleared otherwise.
V, C: Unchanged.
●
Classification
Logical calculation instruction, Read/Modify/Write type instruction
●
Execution Cycles
1+2a cycles
●
Instruction Format
N
Z
V
C
C
C
-
-
MSB
LSB
1
0
0
0
0
1
0
1
Rj
Ri