Fujitsu FR81 사용자 설명서
CM71-00105-1E
FUJITSU MICROELECTRONICS LIMITED
131
FR81 Family
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.14
7.14
ASR (Arithmetic shift to the Right Direction)
Makes an arithmetic right shift of the word data in Ri by Rj bits, stores the result to Ri.
Only the lower 5 bits of Rj, which designates the size of the shift, are valid and the shift
range is 0 to 31 bits.
Only the lower 5 bits of Rj, which designates the size of the shift, are valid and the shift
range is 0 to 31 bits.
●
Assembler Format
ASR Rj, Ri
●
Operation
Ri >> Rj
→ Ri
●
Flag Change
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is zero, cleared otherwise.
V: Unchanged.
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
●
Classification
Shift instructions, Instruction with delayed slot
●
Execution Cycles
1 cycle
●
Instruction Format
N
Z
V
C
C
C
-
C
MSB
LSB
1
0
1
1
1
0
1
0
Rj
Ri