Fujitsu FR81S 사용자 설명서
CHAPTER 50: RAM DIAGNOSIS FUNCTION
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAM DIAGNOSIS FUNCTION
FUJITSU SEMICONDUCTOR CONFIDENTIAL
23
4.11. TEST Error Address Register 0 BACKUP-RAM :
TEAR0A
This section explains the bit structure of TEST Error Address Register 0 BACKUP-RAM.
If an error occurs during RAM diagnosis for Backup RAM, TEST error address register 0 (TEAR0A) holds
the relevant address.
•
TEAR0A: Address 3030
H
(Access: Byte, Half-word, Word)
31
30
29
28
27
26
25
24
BIT
TER2
TER1
TER0
Reserved
0
0
0
0
0
0
0
0
Initial values
R, WX
R, WX
R, WX
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
Attributes
23
22
21
20
19
18
17
16
BIT
Reserved
0
0
0
0
0
0
0
0
Initial values
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
Attributes
15
14
13
12
11
10
9
8
BIT
Reserved
D10
D9
D8
0
0
0
0
0
0
0
0
Initial values
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R, WX
R, WX
R, WX
Attributes
7
6
5
4
3
2
1
0
BIT
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Initial values
R, WX
R, WX
R, WX
R, WX
R, WX
R, WX
R, WX
R, WX
Attributes
[bit31 to bit29] TER2 to TER0: Diagnosis error factor specification bits
During RAM diagnosis for Backup RAM, these bits hold a diagnosis pattern for which the error occurred.
D10 to D0 are valid only when one of the bits is set to "1".
TER2
TER1
TER0
Function
0
0
0
D10 to D0 are invalid with no error generated
-
-
1
An error occurs during march diagnosis
-
1
-
An error occurs during checker diagnosis
1
-
-
An error occurs during unique diagnosis
These bits are initialized (cleared to "000") by hardware, using the RAM diagnosis start instruction as the
trigger.
MB91520 Series
MN705-00010-1v0-E
2144