Motorola MVME5100 사용자 설명서

Functional Description

http://www.motorola.com/computer/literature

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PPC1-Bug>md feff0000

FEFF0000 10574801 00030000 00A0FFF6 00000000 .W................

FEFF0010 000000BE 00000000 00000000 00000000 ....................

PPC1-Bug>md feff0060

FEFF0060 000FFFFF 0000FFFF 000FFFFF 0000FFFF ....................

FEFF0070 03FE0000 00000000 00000000 FFFFFFFF ....................

PPC1-Bug>mw feff0068 55;b

Effective address: FEFF0068

Effective data : 55

PPC1-Bug>md feff0060

FEFF0060 000FFFFF 0000FFFF 004FFFFF 0000FFFF ........O...........

FEFF0070 03FE0000 00000000 00000000 FFFFFFFE ....................

PPC1-Bug>mw feff0068 aa0f5555

Effective address: FEFF0068

Effective data: : AA0F5555

PPC1-Bug>md feff0060

FEFF0060 000FFFFF 0000FFFF 000F5555 00005555 ...........UU..UU...

FEFF0070 03FE0000 00000000 00000000 FFFFFFFE ....................

PPC1-Bug>

The PHB has a mechanism that detects when there is a possible resource 
contention problem (i.e., deadlock) as a result of overlapping PPC and PCI 
initiated transactions. The PPC Slave, PCI Slave, and PCI Master 
functions contain the logic needed to implement this feature.

The PCI Slave and the PPC Slave contribute to this mechanism in the 
following manner. Each slave function will issue a stall signal to the PCI 
Master anytime it is currently processing a transaction that must have 
control of the opposing bus before the transaction can be completed. The 
events that activate this signal are:

❏

Read cycle with no read data in the FIFO

❏

Non-posted write cycle

❏

Posted write cycle and FIFO full