사용자 설명서차례Contents7List of Figures15List of Tables17About This Manual21Summary of Changes24Overview of Contents24Comments and Suggestions25Conventions Used in This Manual25Terminology26Product Data and Memory Maps29Introduction29Memory maps32Processor Memory Map32Default Processor Memory Map32Processor Memory Map33PCI Memory Map35VME Memory Map35PCI Local Bus Memory Map36VMEbus Memory Map36System Bus36Processors37Processor Type Identification37Processor PLL Configuration37L2 Cache37L2 Cache SRAM Size38Cache Speed38FLASH Memory38ECC Memory39P2 I/O Modes39Serial Presence Detect (SPD) Definitions40Hawk ASIC40Hawk I2C interface and configuration information41Vital Product Data (VPD) and Serial Presence Detect (SPD) Data42PCI Local Bus43PCI Arbitration Assignments for Hawk ASIC43The Ethernet Controller44PMC/PCI Expansion Slots45The Universe ASIC45PCI Configuration Space47Hawk External Register Bus Address Assignments49MVME5100 Hawk External Register Bus Summary49Dual TL16C550 UARTs51Status Register52MODFAIL Bit Register53MODRST Bit Register54TBEN Bit Register55NVRAM/RTC & Watchdog Timer56Software Readable Header/Switch Register (S1)57Geographical Address Register (VME board)58Extended Features Register 159Board Last Reset Register60Extended Features Register 261IPMC7xx ISA Bus Resources62W83C554 PIB Registers62PC87308VUL Super I/O (ISASIO) Strapping62Z85230 ESCC and Z8536 CIO Registers and Port Pins63Z8536/Z85230 Registers63Z8536 CIO Port Pins64ISA DMA Channels67Hawk PCI Host Bridge & Multi- Processor Interrupt Controller69Introduction69Overview69Features69Block Diagram71Functional Description72Architectural Overview72PPC Bus Interface73PPC Address Mapping74PPC Slave75PPC FIFO77PPC Master78PPC Arbiter83PPC Parity85PPC Bus Timer86PCI Bus Interface87PCI Address Mapping87PCI Slave90PCI FIFO94PCI Master94Generating PCI Cycles97PCI Arbiter102Endian Conversion106When PPC Devices are Big-Endian106When PPC Devices are Little Endian107PHB Registers108Error Handling109Watchdog Timers110PCI/PPC Contention Handling113Transaction Ordering116PHB Hardware Configuration117Multi-Processor Interrupt Controller (MPIC)119MPIC Features:119Architecture119External Interrupt Interface120CSR’s Readability121Interrupt Source Priority121Processor’s Current Task Priority122Nesting of Interrupt Events122Spurious Vector Generation122Interprocessor Interrupts (IPI)1238259 Compatibility123Hawk Internal Errror Interrupt123Timers124Interrupt Delivery Modes124Block Diagram Description125Program Visible Registers127Interrupt Pending Register (IPR)127Interrupt Selector (IS)127Interrupt Request Register (IRR)128In-Service Register (ISR)128Interrupt Router128Programming Notes130External Interrupt Service130Reset State131Operation132Interprocessor Interrupts132Dynamically Changing I/O Interrupt Configuration132EOI Register133Interrupt Acknowledge Register1338259 Mode133Current Task Priority Level133Architectural Notes134Effects of Interrupt Serialization134Registers135PPC Registers136Vendor ID/Device ID Registers138Revision ID Register138General Control-Status/Feature Registers139PPC Arbiter/PCI Arbiter Control Registers141Hardware Control-Status/Prescaler Adjust Register145PPC Error Test/Error Enable Register147PPC Error Status Register150PPC Error Address Register152PPC Error Attribute Register153PCI Interrupt Acknowledge Register155PPC Slave Address (0,1 and 2) Registers156PPC Slave Offset/Attribute (0, 1 and 2) Registers157PPC Slave Address (3) Register158PPC Slave Offset/Attribute (3) Registers159WDTxCNTL Registers160WDTxSTAT Registers164General Purpose Registers164PCI Registers165Vendor ID/ Device ID Registers166PCI Command/ Status Registers167Revision ID/ Class Code Registers169Header Type Register169MPIC I/O Base Address Register170MPIC Memory Base Address Register170PCI Slave Address (0,1,2, and 3) Registers171PCI Slave Attribute/ Offset (0,1,2 and 3) Registers172CONFIG_ADDRESS Register174CONFIG_DATA Register177MPIC Registers178MPIC Registers178Feature Reporting Register181Global Configuration Register182Vendor Identification Register184Processor Init Register184IPI Vector/Priority Registers185Spurious Vector Register186Timer Frequency Register186Timer Current Count Registers187Timer Basecount Registers188Timer Vector/Priority Registers189Timer Destination Registers190External Source Vector/Priority Registers190External Source Destination Registers192Hawk Internal Error Interrupt Vector/Priority Register193Hawk Internal Error Interrupt Destination Register194Interprocessor Interrupt Dispatch Registers194Current Task Priority Registers195Interrupt Acknowledge Registers195End-of-Interrupt Registers196System Memory Controller (SMC)197Introduction197Overview197Bit Ordering Convention197Features197Block Diagrams198Functional Description202SDRAM Accesses202Four-beat Reads/Writes202Single-beat Reads/Writes202Address Pipelining202Page Holding203SDRAM Speeds203SDRAM Organization205PPC60x Bus Interface205Responding to Address Transfers205Completing Data Transfers205PPC60x Data Parity206PPC60x Address Parity206Cache Coherency207Cache Coherency Restrictions207L2 Cache Support207SDRAM ECC207Cycle Types207Error Reporting208Error Logging209ROM/Flash Interface210ROM/Flash Speeds215I2C Interface218I2C Byte Write219I2C Random Read221I2C Current Address Read223I2C Page Write225I2C Sequential Read227Refresh/Scrub230CSR Accesses230External Register Set230Chip Configuration231Programming Model231CSR Architecture231Register Summary232Detailed Register Bit Descriptions234Vendor/Device Register235Revision ID/General Control Register235SDRAM Enable and Size Register (Blocks A, B, C, D)237SDRAM Base Address Register (Blocks A/B/C/D)239CLK Frequency Register240ECC Control Register242Error Logger Register246Error_Address Register248Scrub/Refresh Register248Scrub Address Register249ROM A Base/Size Register250ROM B Base/Size Register253ROM Speed Attributes Registers255Data Parity Error Log Register257Data Parity Error Address Register258Data Parity Error Upper Data Register258Data Parity Error Lower Data Register259I2C Clock Prescaler Register260I2C Control Register260I2C Status Register261I2C Transmitter Data Register262I2C Receiver Data Register263SDRAM Enable and Size Register (Blocks E,F,G,H)263SDRAM Base Address Register (Blocks E/F/G/H)264SDRAM Speed Attributes Register265Address Parity Error Log Register267Address Parity Error Address Register26832-Bit Counter269External Register Set269tben Register270Software Considerations271Programming ROM/Flash Devices271Writing to the Control Registers271Initializing SDRAM Related Control Registers272SDRAM Speed Attributes272SDRAM Size273I2C EEPROMs273SDRAM Base Address and Enable273SDRAM Control Registers Initialization Example274Optional Method for Sizing SDRAM280ECC Codes283Hawk Programming Details285Introduction285PCI Arbitration285Hawk MPIC External Interrupts2858259 Interrupts287Exceptions289Sources of Reset289Soft Reset289CPU Reset289Error Notification and Handling290Endian Issues291Processor/Memory Domain293MPIC’s Involvement293PCI Domain293Related Documentation295Motorola Computer Group Documents295Manufacturers’ Documents296Related Specifications298MVME5100 VPD Reference Information299Vital Product Data (VPD) Introduction299How to Read the VPD Information299How to Modify the VPD Information300What Happens if the VPD Information is Corrupted?301How to Fix Corrupted VPD Information301What if Your Board Has the Wrong VPD?301How to Fix Wrong VPD Problems301VPD Definitions - Packet Types302VPD Definitions - Product Configuration Options Data305VPD Definitions - FLASH Memory Configuration Data307VPD Definitions - L2 Cache Configuration Data308VPD Definitions - VPD Revision Data310Configuration Checksum Calculation Code312Serial Presence Detect (SPD) Checksum Calculation313VMEbus Mapping Example315Introduction315Index319크기: 1.38메가바이트페이지: 330Language: English매뉴얼 열기