Motorola MVME5100 사용자 설명서

Functional Description

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3-7

Further savings comes when the new address is close enough to a previous 
one that it falls within an open page in the SDRAM array. When this 
happens, the SMC can transfer the data for the next cycle without having 
to wait to activate a new page in SDRAM. In the SMC this feature is 
referred to as page holding.

The SDRAM that the Hawk ASIC controls use the 60x clock. The SMC 
can be configured to operate at several different 60x clock frequencies 
using SDRAMs that have various speed characteristics. The bits that 
control this configuration are located in the SDRAM Speed Attributes 
Register, which is described in the Register portion of this section. Refer 
to 

 for some specific timing numbers.

Table 3-1.  60x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100 

4-Beat Read after idle,

SDRAM Bank Inactive

10-1-1-1

4-Beat Read after idle,

SDRAM Bank Active - Page Miss

12-1-1-1

4-Beat Read after idle,

SDRAM Bank Active - Page Hit

7-1-1-1

4-Beat Read after 4-Beat Read,

SDRAM Bank Active - Page Miss

5-1-1-1

4-Beat Read after 4-Beat Read,

SDRAM Bank Active - Page Hit

2.5-1-1-1

2.5-1-1-1 is an average of 2-
1-1-1 half of the time and 3-
1-1-1 the other half.

4-Beat Write after idle,

SDRAM Bank Active or Inactive

4-1-1-1

4-Beat Write after 4-Beat Write,

SDRAM Bank Active - Page Miss

6-1-1-1