Motorola MVME5100 사용자 설명서
Programming Model
http://www.motorola.com/computer/literature
3-71
3
swr_dpl
swr_dpl causes the SMC to always wait until four clocks after
the write command portion of a single write before allowing a
precharge to occur. This function may not be required. If such is
the case, swr_dpl can be cleared by software.
the write command portion of a single write before allowing a
precharge to occur. This function may not be required. If such is
the case, swr_dpl can be cleared by software.
tdp
tdp determines the minimum number of clock cycles that the
SMC assumes the SDRAM requires to satisfy its Tdp parameter.
When tdp is 0, the minimum time provided for Tdp is 1 clock.
When tdp is 1, the minimum is 2 clocks.
SMC assumes the SDRAM requires to satisfy its Tdp parameter.
When tdp is 0, the minimum time provided for Tdp is 1 clock.
When tdp is 1, the minimum is 2 clocks.
trp
trp determines the minimum number of clock cycles that the
SMC assumes the SDRAM requires to satisfy its Trp parameter.
When trp is 0, the minimum time provided for Trp is 2 clocks.
When trp is 1, the minimum is 3 clocks.
SMC assumes the SDRAM requires to satisfy its Trp parameter.
When trp is 0, the minimum time provided for Trp is 2 clocks.
When trp is 1, the minimum is 3 clocks.
trcd
trcd determines the minimum number of clock cycles that the
SMC assumes the SDRAM requires to satisfy its Trcd
parameter. When trcd is 0, the minimum time provided for Trcd
is 2 clocks. When trcd is 1, the minimum is 3 clocks.
SMC assumes the SDRAM requires to satisfy its Trcd
parameter. When trcd is 0, the minimum time provided for Trcd
is 2 clocks. When trcd is 1, the minimum is 3 clocks.
Address Parity Error Log Register
apelog
apelog is set when a parity error occurs on the PPC60x address
bus during any PPC60x address cycle (TS_ asserted to AACK_
asserted). It is cleared by writing a one to it or by power-up reset.
bus during any PPC60x address cycle (TS_ asserted to AACK_
asserted). It is cleared by writing a one to it or by power-up reset.
ape_tt0-4
ape_tt is the value that was on the TT0-TT4 signals when the
apelog bit was set.
apelog bit was set.
Address
$FEF800E0
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
ap
el
og
0
0
a
p
e_
tt0
a
p
e_
tt1
a
p
e_
tt2
a
p
e_
tt3
a
p
e_
tt4
0
0
0
0
ap
e_ap
0
ap
e_ap
1
ap
e_ap
2
ap
e_ap
3
0
0
0
0
0
0
0
ape_
me
Operation
R/C
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
READ ZERO
Reset
0 P
X
X
0 P
0 P
0 P
0 P
0 P
X
X
X
X
0 P
0 P
0 P
0 P
X
X
X
X
X
X
X
0 PL
X