Samsung S3C2440A 사용자 설명서

The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to 
pass through the synchronizer (Tsyncmax if asynchronous), plus the time for the longest instruction to complete 
(Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data 
abort entry (Texc), plus the time for FIQ entry (Tfiq). At the end of this time ARM920T will be executing the 
instruction at 0x1C.  

Tsyncmax is 3 processor cycles, Tldm is 20 cycles, Texc is 3 cycles, and Tfiq is 2 cycles. The total time is 
therefore 28 processor cycles. This is just over 1.4 microseconds in a system which uses a continuous 20 MHz 
processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher 
priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The minimum latency for 
FIQ or IRQ consists of the shortest time the request can take through the synchronizer (Tsyncmin) plus Tfiq. This 
is 4 processor cycles.  

When the nRESET signal goes LOW, ARM920T abandons the executing instruction and then continues to fetch 
instructions from incrementing word addresses. 

When nRESET goes HIGH again, ARM920T:  

1.  Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value 

of the saved PC and SPSR is not defined. 

2.  Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR's T bit. 

3.  Forces the PC to fetch the next instruction from address 0x00. 

4.  Execution resumes in ARM state.