Texas Instruments TMS320C6452 DSP 사용자 설명서
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3.2.3
Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)
Using the DDR2 Memory Controller
displays the DDR2-533 refresh rate specification.
Table 12. DDR2 Memory Refresh Specification
Symbol
Description
Value
t
REF
Average Periodic Refresh Interval
7.8
μ
s
Therefore, the value for the REFRESH-RATE can be calculated as follows:
REFRESH_RATE = 266.5 MHz
×
7.8
μ
s = 2078.7 = 81Eh
shows the resulting SDRFC configuration.
Table 13. SDRFC Configuration
Field
Value
Function Selection
SR
0
DDR2 memory controller is not in self-refresh mode.
REFRESH_RATE
81Eh
Set to 81Eh DDR2 clock cycles to meet the DDR2 memory refresh rate
requirement.
requirement.
The SDRAM timing 1 register (SDTIM1) and SDRAM timing 2 register (SDTIM2) configure the DDR2
memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in
SDTIM1 and SDTIM2 corresponds to a timing parameter in the DDR2 data sheet specification.
memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in
SDTIM1 and SDTIM2 corresponds to a timing parameter in the DDR2 data sheet specification.
and
display the register field name and corresponding DDR2 data sheet parameter name along
with the data sheet value. These tables also provide a formula to calculate the register field value and
displays the resulting calculation. Each of the equations include a minus 1 because the register fields are
defined in terms of DDR2 clock cycles minus 1. See
displays the resulting calculation. Each of the equations include a minus 1 because the register fields are
defined in terms of DDR2 clock cycles minus 1. See
and
for more information.
Table 14. SDTIM1 Configuration
DDR2 SDRAM Data
Register Field
Sheet Parameter
Data Sheet
Formula (Register
Field
Name
Name
Description
Value (nS)
Field Must Be
≥
)
Value
T_RFC
t
RFC
Refresh cycle time
127.5
(t
RFC
×
f
DDR2_CLK
) - 1
33
T_RP
t
RP
Precharge command to refresh
15
(t
RP
×
f
DDR2_CLK
) - 1
3
or activate command
T_RCD
t
RCD
Activate command to
15
(t
RCD
×
f
DDR2_CLK
) - 1
3
read/write command
T_WR
t
WR
Write recovery time
15
(t
WR
×
f
DDR2_CLK
) - 1
3
T_RAS
t
RAS
Active to precharge command
40
(t
RAC
×
f
DDR2_CLK
) - 1
10
T_RC
t
RC
Activate to Activate command
55
(t
RC
×
f
DDR2_CLK
) - 1
14
in the same bank
T_RRD
t
RRD
Activate to Activate command
10
(t
RRD
×
f
DDR2_CLK
) - 1
3
in a different bank
T_WTR
t
WTR
Write to read command delay
7.5
(t
WTR
×
f
DDR2_CLK
) - 1
1
DSP DDR2 Memory Controller
34
SPRUF85 – October 2007