Texas Instruments TMS320C3x 사용자 설명서
Figures
xx
Figures
1–1
TMS320C3x Devices Block Diagram
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2–1
TMS320C30 Block Diagram
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2–2
TMS320C31 Block Diagram
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2–3
TMS320C32 Block Diagram
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2–4
Central Processing Unit (CPU)
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2–5
Memory Organization of the TMS320C30
2–6
Memory Organization of the TMS320C31
2–7
Memory Organization of the TMS320C32
2–8
TMS320C32-Supported Data Types and Sizes and External Memory Widths
2–9
Peripheral Modules
2–10
DMA Controller
3–1
Extended-Precision Register Floating-Point Format
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3–2
Extended-Precision Register Integer Format
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3–3
Status Register (TMS320C30 andTMS320C31)
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3–4
Status Register (TMS320C32 Only)
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3–5
CPU/DMA Interrupt-Enable (IE) Register (TMS320C30 and TMS320C31)
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3–6
CPU/DMA Interrupt-Enable (IE) Register (TMS320C32)
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3–7
TMS320C30 CPU Interrupt Flag (IF) Register
3–8
TMS320C31 CPU Interrupt Flag (IF) Register
3–9
TMS320C32 CPU Interrupt Flag (IF) Register
3–10
Effective Base Address of the Interrupt-Trap Vector Table
3–11
Interrupt and Trap Vector Locations
3–12
I/O Flag (IOF) Register
4–1
TMS320C30 Memory Maps
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4–2
TMS320C31 Memory Maps
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4–3
TMS320C32 Memory Maps
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4–4
TMS320C30 Peripheral Bus Memory-Mapped Registers
4–5
TMS320C31 Peripheral Bus Memory-Mapped Registers
4–6
TMS320C32 Peripheral Bus Memory-Mapped Registers
4–7
Reset, Interrupt, and Trap Vector Locations for the TMS320C30
Microprocessor Mode
Microprocessor Mode
4–8
Reset, Interrupt, and Trap Vector Locations for theTMS320C31
Microprocessor Mode
Microprocessor Mode
4–9
Interrupt and Trap Branch Instructions for the TMS320C31 Microcomputer Mode
4–10
Interrupt and Trap Vector Locations for TMS320C32
4–11
Address Partitioning for Cache Control Algorithm
4–12
Instruction-Cache Architecture