Texas Instruments TMS320C3x 사용자 설명서
DMA Interrupts
7-38
7.7
DMA Interrupts
Interrupts can also trigger DMA read and write operations. This is called
DMA synchronization. The DMA interrupt processing cycle is similar to that of
the CPU. After the pertinent interrupt flag is cleared, the DMA coprocessor
proceeds according to the status of the SYNC bits in the DMA coprocessor
global-control register.
DMA synchronization. The DMA interrupt processing cycle is similar to that of
the CPU. After the pertinent interrupt flag is cleared, the DMA coprocessor
proceeds according to the status of the SYNC bits in the DMA coprocessor
global-control register.
If the interrupt in the CPU/DMA interrupt-enable (IE) register is enabled, the
interrupt controller automatically latches the interrupt and saves it for future
DMA use. The interrupt controller latches the interrupt, clears the flag in the IF
register, and informs the data that an interrupt has occurred. The DMA then pro-
ceeds with the transfer according to the previously configured CPU/DMA prior-
ity. Even if the DMA has not been started, the interrupt latch occurs, and the flag
is cleared, except when the start bits in the DMA control register have the reset
value 00
interrupt controller automatically latches the interrupt and saves it for future
DMA use. The interrupt controller latches the interrupt, clears the flag in the IF
register, and informs the data that an interrupt has occurred. The DMA then pro-
ceeds with the transfer according to the previously configured CPU/DMA prior-
ity. Even if the DMA has not been started, the interrupt latch occurs, and the flag
is cleared, except when the start bits in the DMA control register have the reset
value 00
2
in START bits. DMA reset clears the interrupt internal latch.
7.7.1
DMA Interrupt Control Bits
Two registers contain bits used to control DMA interrupt operation:
-
CPU/DMA interrupt-enable register (IE). All DMA interrupts are controlled
by the most significant 16 bits in the IE register and by the SYNC bits of
the DMA channel control registers (see Section 12.3.3,
by the most significant 16 bits in the IE register and by the SYNC bits of
the DMA channel control registers (see Section 12.3.3,
DMA Registers,
on page 12-51). The DMA interrupts are not dependent upon ST(GIE) and
are local to the DMA.
are local to the DMA.
-
The DMA channel control register. Each DMA coprocessor channel uses
a channel control register to determine its mode of operation. This register
is shown in Section 12.3.3.
a channel control register to determine its mode of operation. This register
is shown in Section 12.3.3.
The IE is broken into several subfields that determine which interrupts can be
used to control the synchronization for each DMA channel. For example, the bits
in each of these fields allow you to select whether a DMA channel is synchro-
nized to a port, a timer, or an external interrupt pin. Note that the ’C32 has two
DMA channels while the ’C30 and ’C31 have a single DMA channel.
used to control the synchronization for each DMA channel. For example, the bits
in each of these fields allow you to select whether a DMA channel is synchro-
nized to a port, a timer, or an external interrupt pin. Note that the ’C32 has two
DMA channels while the ’C30 and ’C31 have a single DMA channel.
See Section 3.1.8,
CPU/DMA Interrupt-Enable Register (IE), on page 3-9, for
a description of the IE.