Texas Instruments TMS320C3x 사용자 설명서
Decode/address
generation held
until AR write is
completed
generation held
until AR write is
completed
ARs written
Pipeline Conflicts
8-7
Pipeline Operation
is loaded, and a different auxiliary register is used on the next instruction. Since
the decode stage needs the result of the write to the auxiliary register, the
decode of this second instruction is delayed two cycles. Every time the decode
is delayed, a refetch of the program word is performed; the ADDF is fetched
three times. Since these are actual refetches, they can cause not only conflicts
with the DMA controller but also cache hits and misses.
the decode stage needs the result of the write to the auxiliary register, the
decode of this second instruction is delayed two cycles. Every time the decode
is delayed, a refetch of the program word is performed; the ADDF is fetched
three times. Since these are actual refetches, they can cause not only conflicts
with the DMA controller but also cache hits and misses.
A post-/preincrement/decrement of an AR register in an instruction is not
considered a write to a register. A write is in the form of an LDF, LDI, LDII, or
DB instruction.
considered a write to a register. A write is in the form of an LDF, LDI, LDII, or
DB instruction.
Example 8–3. Write to an AR Followed by an AR for Address Generation
LDI
7,AR2
; 7
→
AR2
NEXT
MPYF
*AR2,R0
; Decode delayed 2 cycles
ADDF
FLOAT
FLOAT
Pipeline Operation
PC
Fetch
Decode
Read
Execute
n
LDI
—
—
—
n+1
MPYF
LDI
—
—
n+2
ADDF
MPYF
LDI
—
n+2
ADDF
MPYF
(nop)
LDI 7,AR2
n+2
ADDF
MPYF
(nop)
(nop)
n+3
FLOAT
ADDF
MPYF
(nop)
The case for reads of these groups is similar to the cases for writes. If an
instruction must read a member of one of these groups, the use of that particular
group by the decode for the following instruction is delayed until the read is
complete. The registers are read at the start of the execute cycle and require only
a one-cycle delay of the following decode. For four registers (IR0, IR1, BK, or DP),
there is no delay. For all other registers, including the SP, the delay occurs.
instruction must read a member of one of these groups, the use of that particular
group by the decode for the following instruction is delayed until the read is
complete. The registers are read at the start of the execute cycle and require only
a one-cycle delay of the following decode. For four registers (IR0, IR1, BK, or DP),
there is no delay. For all other registers, including the SP, the delay occurs.
Note that an address generation through the use of an AR register (*AR
n,
*++AR
n, *–ARn, etc.) in an instruction is not considered a read.