Texas Instruments TMS320C3x 사용자 설명서
Pipeline Conflicts
8-9
Pipeline Operation
Memory pipeline conflicts consist of the following four types:
Program wait
A program fetch is prevented from beginning.
Program fetch Incomplete A program fetch has begun but is not yet
complete.
Execute only
An instruction sequence requires three CPU
data accesses in a single cycle.
data accesses in a single cycle.
Hold everything
A primary or expansion bus operation must
complete before another one can proceed.
complete before another one can proceed.
These four types of memory conflicts are illustrated in examples and discussed
in the paragraphs that follow.
in the paragraphs that follow.
8.2.3.1
Program Wait
Two conditions can prevent the program fetch from beginning:
-
The start of a CPU data access when:
J
Two CPU data accesses are made to an internal RAM or ROM block,
and a program fetch from the same block is necessary.
and a program fetch from the same block is necessary.
J
One of the external ports is starting a CPU data access, and a program
fetch from the same port is necessary.
fetch from the same port is necessary.
-
A multicycle CPU data access or DMA data access over the external bus
is needed.
is needed.
Example 8–5 illustrates a program wait until a CPU data access completes.
In this case, *AR0 and *AR1 are both pointing to data in RAM block 0, and the
MPYF instruction will be fetched from RAM block 0. This results in the conflict
shown in Example 8–5. Because more than two accesses can be made to
RAM block 0 in a single cycle, the program fetch cannot begin and must wait
until the CPU data accesses are complete.
In this case, *AR0 and *AR1 are both pointing to data in RAM block 0, and the
MPYF instruction will be fetched from RAM block 0. This results in the conflict
shown in Example 8–5. Because more than two accesses can be made to
RAM block 0 in a single cycle, the program fetch cannot begin and must wait
until the CPU data accesses are complete.