Texas Instruments TMS320C3x 사용자 설명서
2-cycle DMA
access
Pipeline Conflicts
8-11
Pipeline Operation
Example 8–6. Program Wait Due to Multicycle Access
ADDF
; code in internal memory
MPY
; code in internal memory
SUBF
; code in internal memory
CALL
; code in external memory
Pipeline Operation
PC
Fetch
Decode
Read
Execute
n
ADDF
—
—
—
n+1
MPYF
ADDF
—
—
n+2
SUBF
MPYF
ADDF
—
n+3
(wait)
SUBF
MPYF
ADDF
n+3
CALL
(nop)
SUBF
MPYF
n+4
—
CALL
(nop)
SUBF
8.2.3.2
Program Fetch Incomplete
A program fetch incomplete occurs when an instruction fetch takes more than
one cycle to complete because of wait states. In Example 8–7, the MPYF and
ADDF are fetched from memory that supports single-cycle accesses. The
SUBF is fetched from memory requiring one wait state. One example that
demonstrates this conflict is a fetch across a bank boundary on the primary
port. See Section 9.5 on page 9-12.
one cycle to complete because of wait states. In Example 8–7, the MPYF and
ADDF are fetched from memory that supports single-cycle accesses. The
SUBF is fetched from memory requiring one wait state. One example that
demonstrates this conflict is a fetch across a bank boundary on the primary
port. See Section 9.5 on page 9-12.