Texas Instruments TMS320C3x 사용자 설명서

Memory Interface Control Registers

9-9

TMS320C30 and TMS320C31 External-Memory Interface

The expansion-bus control register is a 32-bit register that contains control bits
for the expansion bus (see Figure 9–3 and Table 9–4).

Figure 9–3. Expansion-Bus Control Register

2

1

0

SWW

WTCNT

xx

3

4

5

6

7

11–8

15–12

31–16

R/W

R/W

xx

xx

xx

xx

xx

1) xx = reserved bit, read as 0

2) R = read, W = write

Table 9–4. Expansion-Bus Control Register Bits

SWW

11

Software wait mode

In conjunction with the WTCNT, 2-bit field
defines the mode of wait-state generation.
(See Table 9–5.)

WTCNT

111

Software wait mode

This 3-bit field specifies the number of cycles
to use when in software wait mode for the
generation of internal wait state. The range is
0 (WTCNT = 0 0 0) to 7 (WTCNT = 1) H1/H3
cycles. (See Section 9.4.)

After changing the bit fields of the expansion-bus control register, up to three
instructions are fetched before the expansion bus is reconfigured because
the configuration change is performed in the execute stage of the pipeline.