Texas Instruments TMS320C3x 사용자 설명서
Programmable Wait States
9-10
9.4
Programmable Wait States
The ’C3x has its own internal software-configurable ready-generation capability
for each strobe. This software wait-state generator is controlled by configuring
two bit fields in the primary or expansion bus interface control registers.
for each strobe. This software wait-state generator is controlled by configuring
two bit fields in the primary or expansion bus interface control registers.
Use the WTCNT field to specify the number of software wait-states to generate
and use the SWW field to select one of the following four modes of wait-state
generation:
and use the SWW field to select one of the following four modes of wait-state
generation:
-
External RDY wait states are generated solely by the external RDY line
ignoring software wait states.
ignoring software wait states.
-
WTCNT-generated RDY
wtcnt
wait states are generated solely by the soft-
ware wait-state generator ignoring external RDY signals.
-
Logical-AND of RDY and RDY
wtcnt
wait states are generated with a logical
AND of internal and external ready signals. Both signals must occur.
-
Logical-OR of RDY and RDY
wtcnt
wait states are generated with a logical
OR of internal and external ready signals. Either signal can generate the
ready signal.
ready signal.
The four modes are used to generate the internal ready signal, RDY
int
, that
controls accesses. As long as RDY
int
= 1, the current external access is
delayed. When
RDY
int
= 0, the current access completes. Since the use of
programmable wait states for both external interfaces is identical, only the
primary bus interface is described in the following paragraphs.
primary bus interface is described in the following paragraphs.
RDY
wtcnt
is an internally-generated ready signal. When an external access is
begun, the value in WTCNT is loaded into a counter. WTCNT can be any value
from 0 through 7. The counter is decremented every H1/H3 clock cycle until
it becomes 0. Once the counter is set to 0, it remains set to 0 until the next
access. While the counter is nonzero, RDY
from 0 through 7. The counter is decremented every H1/H3 clock cycle until
it becomes 0. Once the counter is set to 0, it remains set to 0 until the next
access. While the counter is nonzero, RDY
wtcnt
= 1. While the counter is 0,
RDY
wtcnt
= 0.
Table 9–5 shows the truth table for each value of SWW and the different
combinations of RDY, RDY
combinations of RDY, RDY
wtcnt
, and RDY
int
.
Note:
At reset, the ’C3x is programmed with seven wait states for each external
memory access. These wait states are inserted to ensure the system can
function with slow memories. To maximize system performance when acces-
sing external memories, you need to decrease the number of wait states.
memory access. These wait states are inserted to ensure the system can
function with slow memories. To maximize system performance when acces-
sing external memories, you need to decrease the number of wait states.
After changing the wait states, up to three instructions are fetched before the
change in the wait state occurs.
change in the wait state occurs.