Texas Instruments TMS320C3x 사용자 설명서

Parallel ASH3 and STI

13-76

 

count, src2, dst1

||

 src3, 

dst2

If (coun

t 

≥

 0):

src2 << count 

→

 

dst1

Else:

src2 >> |count| 

→

 

dst1

|| 

src3 

→

 

dst2

count register (Rn1, 0 

≤

 

n1  

≤

 7)

src2

indirect (

disp = 0, 1, IR0, IR1)

dst1

register (R

n2, 0  

≤

 

n2  

≤

 7)

src3

register (R

n3, 0  

≤

 

n3  

≤

 7)

dst2

indirect (

disp = 0, 1, IR0, IR1)

This instruction’s operands have been augmented in the following devices:

-

’C31 silicon revision 6.0 or greater

-

’C32 silicon revision 2.0 or greater

src2

indirect (

disp = 0, 1, IR0, IR1) or any CPU register

dst1

register (R

n1, 0 

≤

 

n1 

≤

7)

src3

register (R

n2, 0 

≤

 

n2 

≤

 7)

dst2

indirect (

disp = 0, 1, IR0, IR1)

31

24 23

16

8 7

0

15

1 1 0 1 0 0 1

dst

1

count

src

3

dst

2

src

2

The seven LSBs of the 

count operand register are used to generate the 2s-

complement shift count of up to 32 bits.

If the 

count operand is greater than 0, the src2 operand is left shifted by the

value of the 

count operand. Low-order bits shifted in are zero filled, and high-

order bits are shifted out through the C bit.

Arithmetic left shift:

C 

←

 src2 

←

 0

If the 

count operand is less than 0, the src2 operand is right hifted by the abso-

lute value of the 

count operand. The high-order bits of the src2 operand are

sign extended as they are right shifted. Low-order bits are shifted out through
the C bit.