Texas Instruments TMS320C3x 사용자 설명서

 Parallel ASH3 and STI

13-77

  Assembly Language Instructions

Arithmetic right shift:

sign of 

src2 

→

 

src2 

→

 C

If the 

count operand is 0, no shift is performed, and the C bit is set to 0. The

count and dst operands are assumed to be signed integers.

All registers are read at the beginning and loaded at the end of the execute
cycle. If one of the parallel operations (STI) reads from a register and the oper-
ation being performed in parallel (ASH3) writes to the same register, STI ac-
cepts the contents of the register as input before it is modified by the ASH3.

If 

src2 and dst2 point to the same location, src2 is read before the write to dst2.

1

These condition flags are modified only if the destination register is R7 – R0.

Unaffected

1 if an integer overflow occurs; unchanged otherwise

0

MSB of the output

1 if a 0 result is generated; 0 otherwise

1 if an integer overflow occurs; 0 otherwise

Set to the value of the last bit shifted out; 0 for a shift count of 0

Operation is not affected by OVM bit value.